Date: Tuesday 10 March 2020
Time: 14:30 - 16:00
Location / Room: Amphithéâtre Jean Prouve

Chair:
Pierre-Emmanuel Gaillardon, University of Utah, US

Co-Chair:
Michael Niemier, University of Notre Dame, US

The past five decades have witnessed transformations happening at an ever-growing pace thanks to the sustained increase of capabilities of electronics systems. We are now at the dawn of a new revolution where emerging technologies, understand beyond silicon complementary metal oxide semiconductors, are going to further revolutionize the way we design electronics. In this hot topic session, we intend to elaborate on the architectural opportunities and challenges brought by non-standard semiconductor technologies. In addition to provide new perspectives to the DATE community beyond the currently hot novel architectures, such as neuromorphic or in-memory computing, this proposal also serve the purpose of tightening the link between DATE and the EDA community at large with the mission and roles of the IEEE Rebooting Computing Initiative - https://rebootingcomputing.ieee.org.

Time	Label	Presentation Title Authors
14:30	3.1.1	CRYO-CMOS INTERFACES FOR A SCALABLE QUANTUM COMPUTER Authors: Edoardo Charbon1, Andrei Vladimirescu2, Fabio Sebastiano3 and Masoud Babaie3 1EPFL, CH; 2University of California, Berkeley, US; 3TU Delft, NL
14:45	3.1.2	THE N3XT 1,000X FOR THE COMING SUPERSTORM OF ABUNDANT DATA: CARBON NANOTUBE FETS, RESISTIVE RAM, MONOLITHIC 3D Authors: Gage Hills1 and Mohamed M. Sabry2 1Massachusetts Institute of Technology, US; 2Nanyang Technological University, SG
15:00	3.1.3	MULTIPLIER ARCHITECTURES: CHALLENGES AND OPPORTUNITIES WITH PLASMONIC-BASED LOGIC Speaker: Eleonora Testa, EPFL, CH Authors: Eleonora Testa1, Samantha Lubaba Noor2, Odysseas Zografos3, Mathias Soeken1, Francky Catthoor3, Azad Naeemi2 and Giovanni Demicheli1 1EPFL, CH; 2Georgia Tech, US; 3IMEC, BE Download Paper (PDF; Only available from the DATE venue WiFi)
15:15	3.1.4	QUANTUM COMPUTER ARCHITECTURE: TOWARDS FULL-STACK QUANTUM ACCELERATORS Speaker: Koen Bertels, TU Delft, BE Authors: Koen Bertels, Aritra Arkar, T. Hubregtsen, M. Serrao, Abid A. Mouedenne, A. Yadav, A. Krol, Imran Ashraf and Carmen G. Almudever, TU Delft, NL Download Paper (PDF; Only available from the DATE venue WiFi)
15:30	3.1.5	UTILIZING BURIED POWER RAILS AND BACKSIDE PDN TO FURTHER CMOS SCALING BELOW 5NM NODES Authors: Odysseas Zografos, Sudhir Patli, Satadru Sarkar, Bilal Chehab, Doyoung Jang, Rogier Baert, Peter Debacker, Myung-Hee Na and Julien Ryckaert, IMEC, BE
15:45	3.1.6	A RRAM-BASED FPGA FOR ENERGY-EFFICIENT EDGE COMPUTING Authors: Xifan Tang, Ganesh Gore, Patsy Cadareanu, Edouard Giacomin and Pierre-Emmanuel Gaillardon, University of Utah, US Download Paper (PDF; Only available from the DATE venue WiFi)
16:00		End of session