Technical Programme Committee 2020

Track D: Design Methods and Tools (click to open)

addresses design automation, design tools and hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms, and tools related to the use of computers in designing complete systems. The track’s focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments.

Track Chair:

Topics

D1 System Specification and Modeling (click to open)

Chair: Frederic Mallet, University of Nice Sophia Antipolis, FR, Contact

Co-Chair: Gianluca Palermo, Politecnico di Milano, IT, Contact

Topic Members (click to open)

Patricia Derler, National Instruments, US, Contact
Abdoulaye Gamatie, LIRMM / CNRS / UM2, FR, Contact
Sabine Glesner, Technische Universität Berlin, DE, Contact
Jörn W. Janneck, Lund University, SE, Contact
Matthias Jung, Fraunhofer IESE, DE, Contact
Julio Medina, niversidad de Cantabria, ES, Contact

Modeling and specification methodologies for complex HW-SW systems; requirements engineering; multi-domain/multi-criteria specifications; meta-modeling; design and specification languages; application and workload models; models of computation and their (static) analysis; models of concurrency and communication; model- and component-based design; refinement and validation flows; modeling and analysis of functional and non-functional system properties; modeling of system adaptivity; time and performance modeling; predictive and learning-based models; system-level platform and architecture models and simulation; heterogeneous system models.

D2 System-Level Design Methodologies and High-Level Synthesis (click to open)

Chair: Yuko Hara-Azumi, Tokyo Institute of Technology, JP, Contact

Co-Chair: Philippe Coussy, Universite de Bretagne-Sud / Lab-STICC, FR, Contact

Topic Members (click to open)

Alberto A. Barrio del Garcia, Universidad Complutense de Madrid: UCM, ES, Contact
Michael Glaß, Ulm University, DE, Contact
Soonhoi Ha, Seoul National University, KR, Contact
Luciano Lavagno, Politecnico di Torino, IT, Contact
Razvan Nane, TU Delft, NL, Contact
Preeti Panda, IIT Delhi, IN, Contact
Sudeep Pasricha, Colorado State University, US, Contact
Christian Pilato, Politecnico di Milano, IT, Contact
Donatella Sciuto, Politecnico di Milano, IT, Contact
jason xue, City University of Hong Kong, HK, Contact
Wei Zhang, Hong Kong University of Science and Technology, CN, Contact
Zhiru Zhang, Cornell University, US, Contact

High-level and system-level synthesis techniques; high-level design languages; system-level models for design and optimization; methods for HW-SW co-design and partitioning; control and data flow analysis; HW-SW interface and protocol communication synthesis; interface-based and correct-by-construction designs; high-level and system-level scheduling, allocation, and binding techniques; design space exploration and systematic optimization techniques for high-level synthesis and system-level design; platform-based and reuse-centric design methods and architectures; HW/SW design patterns for multi-processor system-on-chip (MPSoC); system-level design of heterogeneous computing systems.

D3 System Simulation and Validation (click to open)

Chair: Graziano Pravadelli, University of Verona, IT, Contact

Co-Chair: Avi Ziv, IBM Research - Haifa, IL, Contact

Topic Members (click to open)

Mingsong Chen, East China Normal University, CN, Contact
Flavio M. de Paula, IBM Corporation, US, Contact
Masahiro Fujita, University of Tokyo, JP, Contact
Daniel Grosse, University of Bremen/DFKI GmbH, DE, Contact
Katell Morin-Allory, TIMA Laboratory, FR, Contact
Jaan Raik, Tallinn University of Technology, Es, Contact

Simulation-based and semi-formal validation and verification of SoCs, cyber-physical systems and emerging architectures at any level, from system to circuit, including, in particular, testbench and assertion generation and qualification, coverage metrics for functional validation and verification, checker synthesis and optimization, multi-domain and mixed-critical simulation techniques, acceleration-driven and emulation-based approaches for verification and validation, simulation-based pre- and post-silicon debugging, validation and verification for IoT and cloud infrastructures and semi-formal methods for security verification and detection of vulnerabilities, with or without the employment of artificial intelligence or machine learning techniques.

D4 Formal Methods and Verification (click to open)

Chair: Alessandro Cimatti, Fondazione Bruno Kessler, IT, Contact

Co-Chair: Anna Slobodova, Centaur Technology, US, Contact

Topic Members (click to open)

Stefano Quer, Politecnico di Torino, IT, Contact
Heinz Riener, EPFL, CH, Contact
Christoph Scholl, University Freiburg, DE, Contact
yvizel cs [dot] technion [dot] ac [dot] il, Contact
Georg Weissenbacher, Vienna University of Technology, AT, Contact

Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction, decomposition techniques and compositional reasoning); core algorithmic technologies supporting formal verification such as SAT and SMT techniques; formal verification of hardware (including IPs, SoCs, and cores), software, HW-SW systems, timed, or hybrid systems; semi-formal verification techniques; integration of verification into design flows; challenges of multi-cores (as verification targets or as verification host platforms); formal synthesis.

DT5 Design and Test for Analog and Mixed-Signal Circuits and Systems, and MEMS (click to open)

Chair: Manuel Barragan, TIMA Laboratory, FR, Contact

Co-Chair: mphlin nctu [dot] edu [dot] tw, Contact

Topic Members (click to open)

Günhan Dündar, Boğaziçi University, TR, Contact
helmut [dot] graeb tum [dot] de, Contact
Gildas Leger, Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES, Contact
Marie-Minerve Louerat, CNRS and University Pierre et Marie Curie, FR, Contact
Shahriar Mirabbasi, University of British Columbia, CA, Contact
Manoj Sachdev, University of Waterloo, CA, Contact
zhengzhang ece [dot] ucsb [dot] edu, Contact

Analog and mixed-signal architecture, system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; innovative circuit topologies and architectures; analog and mixed-signal IC design; MEMS; design for manufacturability and design for yield; design for reliability; self-healing and self-calibration; test generation; fault modeling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics; verification and simulation of analog and mixed-signals.

DT6 Design and Test of Secure Systems (click to open)

Chair: Ilia Polian, University of Stuttgart, DE, Contact

Co-Chair: Lejla Batina, Radboud University Nijmegen, NL, Contact

Topic Members (click to open)

Georg T. Becker, Horst Görtz Institute for IT-Security, Ruhr-University Bochum, DE, Contact
Anupam Chattopadhyay, Nanyang Technological University, SG, Contact
Ricardo Chaves, Instituto de Engenharia de Sistemas e Computadores, PT, Contact
Viktor Fischer, Hubert Curien Laboratory, FR, Contact
Jorge Guajardo, Bosch Research and Technology Center, Robert Bosch LLC, US, Contact
Annelie Heuser, Univ Rennes, Inria, CNRS, France, FR, Contact
Mike Hutter, Cryptography Research Inc., US, Contact
Elif Kavun, University of Sheffield, GB, Contact
Kerstin Lemke-Rust, Bonn-Rhein-Sieg University of Applied Sciences, DE, Contact
Nele Mentens, KU Leuven, BE, Contact
Stjepan Picek, Faculty of Electrical Engineering and Computing, HR, Contact
Francesco Regazzoni, ALaRI, CH, Contact
Kazuo Sakiyama, The University of Electro-Communications, JP, Contact
Patrick Schaumont, ECE Department Worcester Polytechnic Institute, US, Contact
Matthias Schunter, Intel, DE, Contact
Johanna Sepúlveda, Airbus Defence and Space, DE, Contact
ruggero [dot] susella st [dot] com, Contact
vincent [dot] verneuil nxp [dot] com, Contact

Hardware security primitives, including: cryptographic methods; side channel analysis (includling modeling and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators; HW Trojans (attacks, detection, or countermeasures); design-for-trust; test infrastructures for secure devices; trusted manufacturing; counterfeit detection and avoidance; HW tampering attacks and protection; modeling and countermeasures for fault attacks; interplay between machine learning and security.

D7 Network on Chip and Communication-Centric Design (click to open)

Chair: Romain Lemaire, CEA-Leti, FR, Contact

Co-Chair: Li-Shiuan Peh, Professor, National University of Singapore, SG, Contact

Topic Members (click to open)

Daniel Chillet, INRIA, FR, Contact
Jean-Philippe Diguet, Lab-STICC, FR, Contact
Paul Gratz, Texas A&M university, US, Contact
Gabriela Nicolescu, Ecole Polytechnique de Montréal, CA, Contact
Vassos Soteriou, Cyprus University of Technology, CY, Contact
Jiang Xu, Hong Kong University of Science and Technology, HK, Contact
Davide Zoni, Politecnico di Milano, IT, Contact

Architecture, design methodologies, modeling and simulation techniques for intra- and inter-chip interconnects, NoC and communication-centric design, including: topology, switching, routing and flow control; communication-aware frameworks for Quality-of-Service, security, robustness, power, variability and thermal management; design space exploration frameworks and programming models for communication-centric design; interconnects for domain-specific applications (high performance computing, in-memory computing, machine learning, etc.); design of interconnects using alternative/emerging technologies (photonics, 2.5D/3D, quantum computing, etc.).

D8 Architectural and Microarchitectural Design (click to open)

Chair: Francisco Cazorla, Barcelona Supercomputing Center and IIIA-CSIC, ES, Contact

Co-Chair: Olivier Sentieys, INRIA, FR, Contact

Topic Members (click to open)

Hossein Asadi, Sharif University of Technology, IR, Contact
Jeronimo Castrillon, Technische Universität Dresden, DE, Contact
caroline [dot] collange inria [dot] fr, Contact
zhenman sfu [dot] ca, Contact
Houman Homayoun, George Mason University, US, Contact
Christophe Jego, Bordeaux INP, CNRS IMS, UMR 5218, FR, Contact
Lei Ju, Shandong University, CN, Contact
Georgios Keramidas, Aristotle University of Thessaloniki/Think Silicon S.A., GR, GR, Contact
Leonidas Kosmidis, Barcelona Supercomputing Center (BSC-CNS) and Universitat Politècnica de Catalunya, ES, Contact
lemieux ece [dot] ubc [dot] ca, Contact
Gokhan Memik, Northwestern University, US, Contact
Miquel Pericàs, CHALMERS, SE, Contact
Tanguy Risset, Inria/INSA-Lyon, FR, Contact
Alberto Ros, University of Murcia, ES, Contact
Cristina Silvano, Politecnico di Milano, IT, Contact
Magnus Själander, Norwegian University of Science and Technology, NO, Contact

Architectural and microarchitectural design techniques, including: memory systems; architectural methods for improving power and energy efficiency; multi/many-core architectures; multi-threading techniques and support for parallelism; application-specific processors and accelerators; architectural support for timing predictability.

D9 Low-power, Energy-efficient and Thermal-aware Design (click to open)

Chair: Andrea Calimera, Politecnico di Torino, IT, Contact

Co-Chair: Pascal Vivet, CEA-Leti, FR, Contact

Topic Members (click to open)

Paolo Amato, Micron, IT, Contact
Nadine Azemard, LIRMM, FR, Contact
Yiran Chen, Duke University, US, Contact
mahesh [dot] chowdhary st [dot] com, Contact
Masanori Hashimoto, Osaka University, JP, Contact
Mohamed M. Sabry, Nanyang Technological University, SG, Contact
Alberto Macii, Politecnico di Torino, IT, Contact
Alberto Nannarelli, Technical University, DK, Contact
Davide Rossi, University of Bologna, IT, Contact
Sheldon Tan, UC Riverside, US, Contact
Chi-Ying Tsui, Hong Kong University of Science and Technology, HK, Contact
Rene van Leuken, Delft University of Technology, NL, Contact
Daniel Wong, University of California, Riverside, US, Contact

Theories, tools and methodologies to design electronic systems with low power consumption, high energy efficiency, and correct thermal behavior, ranging from ultra-low power systems (e.g. for portable/wearable applications at the edge of the IoT) to large-scale battery systems (electric vehicles, energy storage systems) and high-performance systems (data-centers and cloud computing). Topics of interest include: solutions applicable to all layers of design (hardware, software and any cross-layers) with emphasis on power modeling and optimization, temperature modeling and prediction, thermal-power-aware optimization, energy-aware design, battery-aware design, including thermal-power-aware optimization for application specific designs (e.g. AI, ML, etc), smart management of heterogeneous energy-sources, energy harvesting for cyber-physical systems.

D10 Approximate Computing (click to open)

Chair: Lukas Sekanina, Brno University of Technology, CZ, Contact

Co-Chair: Tajana Rosing, University of California, San Diego, US, Contact

Topic Members (click to open)

Nikolaos Bellas, University of Thessaly & CERTH, GR, Contact
Benjamin Carrion Schafer, University of Texas at Dallas, US, Contact
Nikil Dutt, University of California Irvine, US, Contact
Andreas Gerstlauer, The University of Texas at Austin, US, Contact
Seokhyeong Kang, Pohang University of Science and Technology, KR, Contact
Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE, Contact
Weiqiang Liu, Nanjing University of Aeronautics and Astronautics, CN, Contact
Fabrizio Lombardi, Northeastern University, US, Contact
Cristiano Malossi, IBM Research - Zurich, CH, Contact
Daniel Menard, INSA Rennes/IETR, FR, Contact
David Novo, French National Centre for Scientific Research (CNRS), FR, Contact
Marco Platzner, University of Paderborn, DE, Contact
Anand Raghunathan, Purdue University, US, Contact
Sotirios Xydis, National Technical University of Athens, GR, Contact

Design techniques enabling and supporting approximate computing at all levels of the computer stack: circuit, architecture, memory, operating system and software level; top-down and bottom-up approaches; cross-level approximation; quality analysis of approximate systems; dynamic approximation; design automation tools for approximate computing and their benchmarking.

D11 Reconfigurable Systems (click to open)

Chair: Philip Brisk, University of California, Riverside, US, Contact

Co-Chair: Suhaib A. Fahmy, University of Warwick, GB, Contact

Topic Members (click to open)

Christos Bouganis, Imperial College London, GB, Contact
Alessandro Cilardo, University of Naples Federico II, IT, Contact
Nachiket Kapre, Nanyang Technological University, SG, Contact
Bogdan Pasca, Intel, FR, Contact
Marco Domenico Santambrogio, Polimi, IT, Contact
Ioannis Sourdis, Chalmers University of Technology, SE, Contact
Stephan Wong, TU Delft, NL, Contact

Reconfigurable computing platforms and architectures; heterogeneous platforms (e.g., including FPGA/GPU/CPU); reconfigurable processors; statically and dynamically reconfigurable systems and components; reconfigurable computing for machine learning, data center and high-performance computing; FPGA architecture; FPGA partial reconfiguration; design methods and tools for reconfigurable computing.

D12 Logical and Physical Analysis and Design (click to open)

Chair: Luis Miguel Silveira, INESC-ID/IST, PT, Contact

Co-Chair: Mathias Soeken, Integrated System Laboratory – EPFL, CH, Contact

Topic Members (click to open)

Luca Amaru, Synopsys, US, Contact
Anna Bernasconi, Universita' di Pisa, IT, Contact
callegaro gmail [dot] com, Contact
Alper Demir, Koc University, TR, Contact
Petr Fišer, Czech Technical University in Prague, FIT, CZ, Contact
Igor L. Markov, University of Michigan, US, Contact
Christos Sotiriou, Department of Electrical and Computer Engineering, University of Thessaly, GR, Contact
Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE, Contact
Bei Yu, The Chinese University of Hong Kong, HK, Contact
Wenjian Yu, Tsinghua University, CN, Contact

Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; logic synthesis for emerging technologies; combined logic synthesis and layout design and characterization; statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automated place-and-route; interconnect- and performance-driven layout; process technology developments; parasitic and variation-aware extraction for on-chip interconnect and passives; macro-modeling, behavioral and reduced order modeling; modeling and analysis of noise due to electromagnetic interaction of signal, power/ground, and substrate.

D13 Emerging Design Technologies for Future Computing (click to open)

Chair: Elena Gnani, Università di Bologna, IT, Contact

Co-Chair: Subhasish Mitra, Stanford University, US, Contact

Topic Members (click to open)

Yuanqing Cheng, Beihang University, CN, Contact
Maria De Souza, University of Sheffield, GB, Contact
Thomas Thomas Ernst, CEA-Leti, FR, Contact
Mariagrazia Graziano, Politecnico di Torino, IT, Contact
Gage Hills, Massachusetts Institute of Technology, US, Contact
rakheja illinois [dot] edu, Contact
Arijit Raychowdhury, Georgia Institute of Technology, US, Contact
Heike Riel, IBM Research - Zurich, CH, Contact
alessio [dot] spessot imec [dot] be, Contact
walter [dot] weber tuwien [dot] ac [dot] at, Contact

Modeling, circuit design, and design automation flows for future computing, including: non-CMOS logic based on emerging devices (e.g., carbon nanotube or graphene based FETs, TFETs, NWFETs, single electron transistors, NEMS etc.); alternative interconnect technologies (e.g., optical, RF, 3D, carbon nanotubes, graphene nanoribbons, spintronics, etc.); monolithic 3D integration (including TSV modeling and design space exploration).

D14 Emerging Design Technologies for Future Memories (click to open)

Chair: Shahar Kvatinsky, Technion, IL, Contact

Co-Chair: Chengmo Yang, University of Delaware, US, Contact

Topic Members (click to open)

joseph [dot] friedman utdallas [dot] edu, Contact
Arne Heittman, RWTH Aachen University, DE, Contact
Yu Hua, Huazhong University of Science and Technology, CN, Contact
Alexandre Levisse, EPFL, CH, Contact
shuangchen [dot] li alibaba-inc [dot] com, Contact
Chenchen Liu, University of Maryland, Baltimore County, US, Contact
Jean-Philippe Noel, CEA-Leti, FR, Contact
Damien Querlioz, IEF - University Paris Sud, FR, Contact
Stefan Slesazeck, NaMLab gGmbH, DE, Contact
Marco Vacca, Politecnico di Torino, IT, Contact
Wujie Wen, Lehigh University, US, Contact
Hao Yu, Southern University of Science and Technology, China, CN, Contact
Weisheng Zhao, Beihang University, CN, Contact
Cheng Zhuo, Zhejiang University, CN, Contact

Modeling, circuit design, and design automation flows for future data storage systems, including non-CMOS memory (e.g., MRAM, STT-RAM, FeRAM, PCRAM, RRAM, OxRAM, quantum dots, etc.); memory-centric architectures (e.g., logic-in-memory, associative memories, non-volatile caches etc.); memory management techniques for emerging memories.

Track A: Application Design (click to open)

is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, real-world implementations, and applications of specific design and test methodologies. Contributions should illustrate innovative or record-breaking designs, which will provide viable solutions in tomorrow’s silicon, embedded systems, and large-scale systems. In topic A8, there is the opportunity to submit 2-page papers that expose industrial research and practice.

Track Chair:

Topics

A1 Power-efficient and Sustainable Computing (click to open)

Chair: Baris Aksanli, San Diego State University, US, Contact

Co-Chair: Jungwook Choi, Hanyang University, KR, Contact

Topic Members (click to open)

Andreas Burg, EPFL, CH, Contact
Thidapat Chantem, Virginia Polytechnic Institute and State University, US, Contact
william fornaciari, Politecnico di Milano - DEIB, IT, Contact
Hai (Helen) Li, Duke University/TUM-IAS, US, Contact
Saibal Mukhopadhyay, Georgia Institute of Technology, US, Contact
Semeen Rehman, TU Wien, AT, Contact
Amit Kumar Singh, University of Essex, GB, Contact

Application design experiences and real implementations of power-efficient systems or circuits with high industrial relevance or high environmental impact, especially targeting ultra-low-power, high-performance, or large-scale computing systems (such as MPSoCs, mobile systems, massively parallel computers, 2D/3D multi-/many-core systems, high-performance computing clusters, data centers, and cloud systems). Topics of interest include: software architectures for energy-efficient computing; virtualization; energy-efficient memory; low-power processors; emerging communication or computing systems (e.g., power-efficient machine learning accelerators); in-memory computing or memristor-based accelerators; heterogeneous computing; resource management techniques; innovative data-center management strategies; SW/OS-level implementations in real systems and data centers; energy-efficient big data management; data centers powered by renewable energy sources and data centers in smart grids.

A2 Robotics and Industry 4.0 (click to open)

Chair: Ulrike Thomas, Technical University of Chemnitz, DE, Contact

Co-Chair: Federica Ferraguti, University of Modena and Reggio Emilia, IT, Contact

Topic Members (click to open)

d [dot] pesch cs [dot] ucc [dot] ie, Contact
anders [dot] robertsson control [dot] lth [dot] se, Contact
matteo [dot] saveriano uibk [dot] ac [dot] at, Contact

Bringing together robotics and machine learning concepts requires research and development efforts in interdisciplinary domains. With Industry 4.0 and its goal of adding utility value through data analytics and optimiztion, the Topic "Robotics and Industry 4.0" will remain at the core of the value creation chain during the next decade. The topic covers the field of robotics on topics from sensors and sensory interpretations to kinematics in motion planning, from distributed software concepts for data collection and analysis to large-scale machine learning algorithms, and sensor-based robot and machine control to safe human-robot interaction concepts.

A3 Automotive Systems and Smart Energy Systems (click to open)

Chair: Sebastian Steinhorst, TUM, DE, Contact

Co-Chair: David Boyle, Imperial College London, GB, Contact

Topic Members (click to open)

Dip Goswami, Eindhoven University of Technology, NL, Contact
Angeliki Kritikakou, University of Rennes 1 / IRISA, FR, Contact
Angeliki Kritikakou, University of Rennes 1 / IRISA, FR, Contact
Massimo Poncino, Politecnico di Torino, IT, Contact
Selma Saidi, TU Dortmund, DE, Contact
Dirk Ziegenbein, Robert Bosch GmbH, DE, Contact

Design experiences for automotive systems, energy-neutral embedded systems, smart energy systems (from uW to microgrid), and related Cyber-Physical applications. Topics of interest include: transient computing; energy harvesting circuits; MEMS; integrated sensors and transducers; RF architectures; innovative concepts for power distribution, energy storage, grid monitoring and high-voltage structures; solutions for runtime system management such as self-diagnostics and repair; design and optimization of energy generation and renewable energy subsystems; battery management and E/E architecture for electric vehicles; in-vehicle networks and system architectures; optimization of system energy efficiency in the context of automotive or smart energy applications.

A4 Augmented Living and Personalized Healthcare (click to open)

Chair: Ioannis Papaefstathiou, School of Electrical and Computer Engineering, Aristotle University of Thessaloniki, GR, Contact

Co-Chair: Daniela De Venuto, Politecnico di Bari, IT, Contact

Topic Members (click to open)

Amir Aminifar, Swiss Federal Institute of Technology Lausanne (EPFL), CH, Contact
Guillermo Botella, Complutense University of Madrid, ES, Contact
Eduardo de la Torre, Universidad Politécnica de Madrid, ES, Contact
Michele Magno, ETH Zurich, CH, Contact
dimitrios [dot] tzovaras iti [dot] gr, Contact

Design experiences covering the use of body area networks, assistive and wearable technologies, edge computing and IoT for healthcare, wellness and augmented living. Topics of interest include: technologies, devices, systems and paradigms (including approximate or significance-driven computing) for ultra-low/zero power systems for personal health and personalized medicine including non-intrusive or implantable miniaturized sensors and actuators, on-board performance optimization and contextualized power-management ; embedded IP and systems for audio, video, and computer vision domains ; intelligent sensor networks, systems, automation and environments for augmented living, assisted living, rehabilitation, healthcare and wellness ; embedded and edge-based machine learning for augmented living.

A5 Secure Systems, Circuits, and Architectures (click to open)

Chair: Lionel Torres, University of Montpellier, FR, Contact

Co-Chair: Cambou Bertrand, Northern Arizona University, US, Contact

Topic Members (click to open)

Aydin Aysu, North Carolina State University, US, Contact
Bossuet Lilian, University of St. Etienne, FR, Contact
Ray Cheung, City University of Hong Kong, HK, Contact
Guillaume Duc, Telecom Paristech, FR, Contact
Basel Halak, University of Southampton, GB, Contact
Ajay Joshi, Boston University, US, Contact
Michail Maniatakos, New York University Abu Dhabi, AE, Contact
Marchand Cedric, Ecole Centrale de Lyon, FR, Contact
Marcel Medwed, NXP Semiconductors Austria GmbH, AT, Contact
Fernando Moraes, PUCRS University, BR, Contact
Nicolas Sklavos, University of Patras, GR, Contact
Ingrid Verbauwhede, imec-COSIC, KU Leuven, BE, Contact

Secure circuits and architectures, with an emphasis on design experiences, real system deployments, applications, and silicon prototypes. Topics of interest include: secure HW architectures; emerging technologies for secure circuits and architectures, novel architectures for embedded cryptography; demonstrations with fault or other physical attacks; embedded processors or co-processors for security; off-chip memories and network-on-chip and secure communication/integrity; demonstrations of HW-enabled security on real systems or prototypes; logic-level security; firmware security.

A6 Self-adaptive and Learning Systems (click to open)

Chair: Antonio Miele, Politecnico di Milano, IT, Contact

Co-Chair: Gilles Sassatelli, LIRMM CNRS / University of Montpellier 2, FR, Contact

Topic Members (click to open)

Woongki Baek, UNIST, KR, Contact
Giovanni Beltrame, École Polytehcnique de Montréal, CA, Contact
Geoff Merrett, University of Southampton, GB, Contact
Andy Pimentel, University of Amsterdam, NL, Contact

Self-adaptive systems, algorithms and techniques for run-time decision-making targeting various optimization goals such as compute performance, energy/power-efficiency or reliability and considering various architectural platforms, such as high-performance compute nodes, power-constrained edge computing technologies and reconfigurable systems. Topics of interests include: adaptive strategies for runtime resource management; application, design and tuning of machine learning techniques for offline and/or online modeling, prediction/forecasting and control of self-adaptive systems; hybrid offline/online techniques for online decision-making; context-aware adaptation strategies and mechanisms; application of diverse data mining, modeling and optimization techniques (control automation, game theory, etc.); design experiences and industrial use-cases of self-adaptive systems possibly based on machine learning techniques.

A7 Applications of Emerging Technologies (click to open)

Chair: Robert Wille, Johannes Kepler University Linz, AT, Contact

Co-Chair: Michael Niemier, University Of Notre Dame, US, Contact

Topic Members (click to open)

Armin Alaghi, University of Washington, US, Contact
kcamsari purdue [dot] edu, Contact
Deliang Fan, Arizona State University, US, Contact
Bastien Giraud, CEA LETI, FR, Contact
Jim Harkin, Ulster University, GB, Contact
Li Jiang, Shanghai Jiao Tong University, CN, Contact
Bing Li, TUM, DE, Contact
yongpan liu, tsinghua university, CN, Contact
Vasilis Pavlidis, University of Manchester, GB, Contact
Martin Albrecht Trefzer, University of York, GB, Contact
Shigeru Yamashita, Ritsumeikan University, JP, Contact
hailongyao tsinghua [dot] edu [dot] cn, Contact
yiyang2006 gmail [dot] com, Contact

Applications of and design methods for systems based on future and emerging technologies. Topics of interest include: neuromorphic and bio-inspired computing systems; bio-MEMS and lab-on-a-chip; emerging models of computation (e.g., quantum computing, reversible logic, approximate computing, stochastic computing); application case studies for emerging technologies (e.g., cryptography, wearable computing, e-textiles, energy-critical systems, etc.).

A8 Industrial Experiences Brief Papers (click to open)

Chair: Norbert Wehn, University of Kaiserslautern, DE, Contact

Co-Chair: Nicolas Ventroux, CEA, LIST, FR, Contact

Topic Members (click to open)

mohamed [dot] s [dot] ibrahim alumni [dot] duke [dot] edu, Contact
Doris Keitel-Schulz, Infineon AG, DE, Contact
Enrico Macii, Politecnico di Torino, IT, Contact
Dionisios Pnevmatikatos, Technical University of Crete, GR, Contact

Short 2-page industrial papers are solicited. Submissions should relate to industrial research and practice, including: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanisms; on-line testing and fault tolerance for industrial applications. Pure product presentations and announcements are strongly discouraged and will not be considered for publication.

Track T: Test and Dependability (click to open)

covers all test, design-for-test, reliability, and designfor-robustness issues, at system-, chip-, circuit-, and device-level for both analogue and digital electronics. Topics of interest also include diagnosis, failure mode analysis, debug and post-silicon validation challenges, and test or fault injection methods addressing system security.

Track Chair:

Topics

T1 Modeling and Mitigation of Defects, Faults, Variability, and Reliability (click to open)

Chair: Arnaud Virazel, LIRMM, FR, Contact

Co-Chair: Bram Kruseman, NXP Semiconductors, NL, Contact

Topic Members (click to open)

Lorena Anghel, Grenoble-Alpes University, FR, Contact
Antonio Rubio, UPC, ES, Contact
Seiji Kajihara, Kyushu Institute of Tech, JP, Contact
Naghmeh Karimi, University of Maryland Baltimore county, US, Contact
Michele Portolan, TIMA, Univesité Grenoble Alpes, FR, Contact
Christian Sauer, Cadence Design Systems GmbH, DE, Contact
Matteo Sonza Reorda, Politecnico di Torino - DAUIN, IT, Contact
Hank Walker, Texas A&M University, US, Contact

Identification, characterization, and modeling of defects, faults, and degradation mechanisms in conventional, advanced, or emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT, etc.); defect-based fault analysis; reliability analysis and modeling at device, circuit, or component level; process yield modeling and enhancement; design-for-manufacturability and design-for-yield; noise and uncertainty modeling at circuit and component level; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations at circuit or component level.

T2 Test Generation, Test Architectures, Design for Test, and Diagnosis (click to open)

Chair: Patrick Girard, LIRMM, FR, Contact

Co-Chair: Bernd Becker, University of Freiburg, DE, Contact

Topic Members (click to open)

Davide Appello, STMicroelectronics, IT, Contact
Paolo Bernardi, Politecnico di Torino, IT, Contact
Artur Jutman, Testonica Lab, EE, Contact
Daniel Tille, Infineon Technologies AG, DE, Contact
Jerzy Tyszer, Poznan University of Technology, PL, Contact
Xiaoqing Wen, Kyushu Institute of Technology, JP, Contact

Test pattern generation for logic and delay faults, defect-based fault models, low-power ICs; fault simulation; test compression; power/thermal issues in test; test generation and test architectures for memories, FPGAs, microprocessors, accelerators, NoC, SoC and 3D ICs; solutions for design-for-test, diagnosis, machine learning for IC testing; BIST; board and system test; volume diagnosis and yield analysis.

T3 Microarchitecture-Level Dependability (click to open)

Chair: Ramon Canal, UPC, ES, Contact

Co-Chair: Stefano Di Carlo, Politecnico di Torino, IT, Contact

Topic Members (click to open)

Nikos Foutris, University of Manchester, GB, Contact
Dimitris Gizopoulos, University of Athens, Department of Informatics & Telecommunications, GR, Contact
Brett Meyer, McGill University, CA, Contact
Dimitris Nikolos, University of Patras, GR, Contact
Ernesto Sanchez, Politecnico di Torino, IT, Contact
Vasileios Tenentes, University of Ioannina, GR, Contact

Micro/architectures for fault-tolerant systems against permanent, transient and soft errors, including (but not limited to) processors, memories and accelerators; micro/architectural solutions for safety- and mission-critical systems; analysis and evaluation of reliability, availability and maintainability at micro/architectural level; hardware/software micro/architectural solutions for fault detection, recovery and aging mitigation.

T4 System-Level Dependability (click to open)

Chair: Maria K. Michael, Electrical and Computer Engineering & KIOS Center of Excellence, University of Cyprus, CY, Contact

Co-Chair: Georgios Karakonstantis, Queen's University Belfast, GB, Contact

Topic Members (click to open)

Luca Cassano, Politecnico di Milano, IT, Contact
Görschwin Fey, Technische Universität Hamburg, DE, Contact
Ernesto Sanchez, Politecnico di Torino, IT, Contact
Rishad Shafik, Newcastle University, GB, Contact
Vasileios Tenentes, University of Ioannina, GR, Contact

HW and SW solutions for dependability at system level; system level error/fault modeling; dependability analysis and evaluation; reliable and fail-safe system design; system-level on-line test and functional safety; runtime system management for dependability; cross-layer solutions; application resilience; high-level synthesis (HLS) dependability, approximate computing for resilient systems, computational intelligence methods (AI/ML) for dependability; system-level solutions for safety- and mission-critical systems, IoT and cloud infrastructures.

DT5 Design and Test for Analog and Mixed-Signal Circuits and Systems, and MEMS (click to open)

Chair: Manuel Barragan, TIMA Laboratory, FR, Contact

Co-Chair: mphlin nctu [dot] edu [dot] tw, Contact

Topic Members (click to open)

Günhan Dündar, Boğaziçi University, TR, Contact
helmut [dot] graeb tum [dot] de, Contact
Gildas Leger, Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES, Contact
Marie-Minerve Louerat, CNRS and University Pierre et Marie Curie, FR, Contact
Shahriar Mirabbasi, University of British Columbia, CA, Contact
Manoj Sachdev, University of Waterloo, CA, Contact
zhengzhang ece [dot] ucsb [dot] edu, Contact

DT6 Design and Test of Secure Systems (click to open)

Chair: Ilia Polian, University of Stuttgart, DE, Contact

Co-Chair: Lejla Batina, Radboud University Nijmegen, NL, Contact

Topic Members (click to open)

Georg T. Becker, Horst Görtz Institute for IT-Security, Ruhr-University Bochum, DE, Contact
Anupam Chattopadhyay, Nanyang Technological University, SG, Contact
Ricardo Chaves, Instituto de Engenharia de Sistemas e Computadores, PT, Contact
Viktor Fischer, Hubert Curien Laboratory, FR, Contact
Jorge Guajardo, Bosch Research and Technology Center, Robert Bosch LLC, US, Contact
Annelie Heuser, Univ Rennes, Inria, CNRS, France, FR, Contact
Mike Hutter, Cryptography Research Inc., US, Contact
Elif Kavun, University of Sheffield, GB, Contact
Kerstin Lemke-Rust, Bonn-Rhein-Sieg University of Applied Sciences, DE, Contact
Nele Mentens, KU Leuven, BE, Contact
Stjepan Picek, Faculty of Electrical Engineering and Computing, HR, Contact
Francesco Regazzoni, ALaRI, CH, Contact
Kazuo Sakiyama, The University of Electro-Communications, JP, Contact
Patrick Schaumont, ECE Department Worcester Polytechnic Institute, US, Contact
Matthias Schunter, Intel, DE, Contact
Johanna Sepúlveda, Airbus Defence and Space, DE, Contact
ruggero [dot] susella st [dot] com, Contact
vincent [dot] verneuil nxp [dot] com, Contact

Hardware security primitives, including: cryptographic methods; side channel analysis (includling modeling and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators; HW trojans (attacks, detection, or countermeasures); design-for-trust; test infrastructures for secure devices; trusted manufacturing; counterfeit detection and avoidance; HW tampering attacks and protection; modeling and countermeasures for fault attacks; machine learning for hardware security evaluation.

Track E: Embedded and Cyber-Physical Systems (click to open)

is devoted to the modelling, analysis, design and deployment of embedded software or embedded/cyber-physical systems. Areas of interest include methods, tools, methodologies and development environments. Emphasis will also be on model-based design and verification, embedded software platforms, software compilation and integration, real-time systems, cyber-physical systems, networked systems, and dependable systems.

Track Chair: Valeria Bertacco, University of Michigan, US, Contact

Topics

E1 Real-time and Dependable Systems (click to open)

Chair: Dionisio de Niz, Carnegie Mellon University, US, Contact

Co-Chair: Liliana Cucu, INRIA, FR, Contact

Topic Members (click to open)

Marko Bertogna, Modena and Reggio Emilia, IT, Contact
Arvind Easwaran, Nanyang Technical University, SG, Contact
Leandro Indrusiak, University of York, GB, Contact
Hyoseung Kim, University of California, Riverside, US, Contact
Giuseppe Lipari, Scuola Superiore Sant'Anna, IT, Contact
martina [dot] maggio control [dot] lth [dot] se, Contact
rmancuso bu [dot] edu, Contact

Real-time performance modeling, analysis and empirical evaluation; Worst-case performance analysis techniques; Worst-case execution time analysis; Real-time schedulability of multicore systems; Mixed-Criticality scheduling; Real-time operating systems, microkernels and software; Use of hardware virtualization techniques in time critical applications, Power-aware real-time systems; Industrial case studies of real-time, networked and dependable systems; Adaptive real-time systems; Dependable systems including safety and criticality; Network control and QoS for embedded applications.

E2 Embedded Systems for Deep Learning (click to open)

Chair: Tulika Mitra, National University of Singapore, SG, Contact

Co-Chair: Luca Carloni, Columbia University, US, Contact

Topic Members (click to open)

Giovanni Ansaloni, USI Lugano, CH, Contact
David Atienza Alonso, Ecole Polytechnique Federale de Lausanne, CH, Contact
mladen [dot] berekovic gmail [dot] com, Contact
Michaela Blott, Xilinx, IE, Contact
Luigi Carro, UFRGS, BR, Contact
Mario R. Casu, Politecnico di Torino, IT, Contact
bita [dot] rouhani microsoft [dot] com, Contact
Anup Das, IMEC, US, Contact
Rolf Drechsler, University of Bremen/DFKI, DE, Contact
Ujjwal Gupta, Intel Corporation, US, Contact
Tushar Krishna, Georgia Institute of Technology, US, Contact
Kyuho Lee, UNIST, KR, Contact
Smail Niar, University of Valenciennes and Hainaut-Cambresis, FR, Contact
Abbas Rahimi, ETH Zurich, CH, Contact
b [dot] reagen3 gmail [dot] com, Contact
Sander Stuijk, Eindhoven University of Technology, NL, Contact
Marian Verhelst, KULeuven - ESAT - MICAS, BE, Contact
Paul Whatmough, Harvard University, US, Contact
Shouyi YIN, Tsinghua University, CN, Contact
Xuan Zhang, Washington University, US, Contact

Hardware and architectures, software and algorithmic approaches for artificial intelligence, machine learning and deep learning; specialized, heterogeneous, and resource-efficient embedded architectures for machine learning; embedded architectures and software for autonomy, automated reasoning, and planning algorithms; approximate architectures for machine learning applications; learning from limited data sets; frameworks for probabilistic and deep learning programming; safe and secure machine learning; novel neural networks architectures and concepts for embedded computing; case studies of machine learning applications implemented on embedded systems.

E3 Model-Based Design, Verification and Security for Embedded Systems (click to open)

Chair: Yliès Falcone, Univ. Grenoble Alpes, Inria, FR, Contact

Co-Chair: Todd Austin, University of Michigan, US, Contact

Topic Members (click to open)

Ezio Bartocci, Vienna University of Technology, AT, Contact
stephanie [dot] delaune irisa [dot] fr, Contact
radu grosu, TU Wien, AT, Contact
mj54 aub [dot] edu [dot] lb, Contact
laurent [dot] mounier univ-grenoble-alpes [dot] fr, Contact

Verification techniques for embedded ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. Modeling, analysis and optimization of non-functional and performance aspects such as security, timing, memory usage, QoS and reliability. Model-based design of software architectures and deployment. Theories, languages and tools supporting model-based design flows covering software, control and physical components. Monitoring and run-time verification of embedded systems. Security attacks, protection and analysis of embedded systems' hardware and software.

E4 Embedded Software Architecture, Compilers and Tool Chains (click to open)

Chair: Sara Vinco, Politecnico di Torino, IT, Contact

Co-Chair: Borzoo Bonakdarpour, Iowa State University, US, Contact

Topic Members (click to open)

Nicola Bombieri, University of Verona, IT, Contact
Sudipta Chattopadhyay, Singapore University of Technology and Design (SUTD), SG, Contact
Frank Hannig, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE, Contact
Ramy Medhat, University of Waterloo, CA, Contact
Anca Molnos, CEA-Leti, Grenoble, FR, Contact
Rodolfo Pellizzoni, University of Waterloo, CA, Contact
Linh Thi Xuan Phan, University of Pennsylvania, US, Contact

Software architectures, programming paradigms, languages, compiler support, software tools, and techniques (e.g., simulators, synthesis tools) targeting embedded heterogeneous systems for domain-specific applications such as IoTs and wearables; embedded software support for approximate computation and FPGA/GPU based accelerators; memory communication protocols and hierarchy management, including caches, scratchpad, and non-volatile memories; code analysis, code optimization/generation to enhance performance, power/energy, code/data size, reliability, security, WCET, etc.; Real-time software, distributed system software, virtualization, and middleware for embedded systems, including resource-awareness, reconfiguration, energy/power management; compiler support for enhanced debugging, profiling, and traceability.

E5 Cyber-Physical Systems Design (click to open)

Chair: Shiyan Hu, Michigan Technological University, US, Contact

Co-Chair: Davide Quaglia, University of Verona, IT, Contact

Topic Members (click to open)

Mohammad Al Faruque, University of California Irvine, US, Contact
Wanli Chang, University of York, GB, Contact
Robert de Simone, INRIA, FR, Contact
Martin Horauer, University of Applied Sciences Technikum Wien, AT, Contact
Wenchao Li, Boston University, US, Contact
Roberto Passerone, University of Trento, IT, Contact

Modeling, design, verification, validation and optimization of Cyber-Physical Systems (CPS) including large-scale and networked CPS as in current Internet-of-Things; safety and security aspects in CPS; software-intensive CPS; data-mining and CPS; autonomous and semi-autonomous CPS and related issues; socio-technical systems (e.g., empowered consumer and organizational behavior in smart grids); cognitive control for CPS; networked and switched control systems (e.g., control/architecture co-design and architecture-aware controller synthesis).