Date: Thursday 12 March 2020
Time: 16:00 - 17:30
Location / Room: Lesdiguières

Chair:
Enrico Macii, Politecnico di Torino, IT

Co-Chair:
Norbert Wehn, TU Kaiserslautern, DE

This session addresses recent industrial experiences covering all Design Levels from Technology up to System Level

Time	Label	Presentation Title Authors
16:00	12.6.1	WAFER-LEVEL TEST PATH PATTERN RECOGNITION AND TEST CHARACTERISTICS FOR TEST-INDUCED DEFECT DIAGNOSIS Authors: Andrew Yi-Ann Huang1, Katherine Shu-Min Li2, Ken Chau-Cheung Cheng3, Ji-Wei Li1, Leon Li-Yang Chen4, Nova Cheng-Yen Tsai1, Sying-Jyan Wang5, Chen-Shiun Lee1, Leon Chou1, Peter Yi-Yu Liao1, Hsing-Chung Liang6 and Jwu E Chen7 1NXP Semiconductors Taiwan Ltd., TW; 2National Sun Yat-sen University, TW; 3NXP Semiconductors Taiwan Ltd, TW; 4National Sun Yat-Sen University, TW; 5National Chung-Hsing University, TW; 6Chung Yuan Christian University, TW; 7National Central University, TW Abstract Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. This paper applies artificial intelligence based pattern recognition techniques to distinguish fab-induced defects from test-induced ones. As a result, test quality, reliability and yield could be improved accordingly. Wafer test data contain site-dependent information regarding test configurations in automatic test equipment, including effective load push force, gap between probe and loadboard, probe tip size, probe-cleaning force, etc. Our method analyzes both the test paths and site-dependent test characteristics to identify test-induced defects. Experimental results achieve 96.83% prediction accuracy of six different NXP products, which show that our methods are both effective and efficient. Download Paper (PDF; Only available from the DATE venue WiFi)
16:15	12.6.2	A METHOD OF VIA VARIATION INDUCED DELAY COMPUTATION Authors: Moonsu Kim1, Yun Heo1, Seungjae Jung1, Kelvin Le2, Jongpil Lee1, Youngmin Shin1, Nathaniel Conos2 and Hanif Fatemi2 1Samsung, KR; 2Synopsys, US Abstract Abstract— As process technologies are scaled down, interconnect delay becomes major component of entire path delay, and vias represent a significant portion of the interconnect delay. In this paper, a novel variation-aware delay computation method for vias is proposed. Our experiments show that this method can reduce over five percent of pessimism in arrival time calculation when it is compared with state-of-the-art solutions. Download Paper (PDF; Only available from the DATE venue WiFi)
16:30	12.6.3	FULLY AUTOMATED ANALOG SUB-CIRCUIT CLUSTERING WITH GRAPH CONVOLUTIONAL NEURAL NETWORKS Speaker: Keertana Settaluri, University of California, Berkeley, US Authors: Keertana Settaluri1 and Elias Fallon2 1University of California, Berkeley, US; 2Cadence Design Systems, US Abstract The design of custom analog integrated circuits is one of the contributing factors in high development cost and increased production time, driving the need for more automation in this space. In automating particular avenues of analog design, it is then crucial to assess the efficacy with which the automation algorithm is able to solve the desired problem. To do this, one must consider four metrics that are especially pertinent in this area: robustness, accuracy, level of automation, and computation time. In this work, we present a framework that bridges the gap between schematic and layout generation, by encapsulating the design intuition needed to create layout through identification of critical sub-circuit structures. Our approach focuses on identifying analog sub-circuits by utilizing Graphical Convolutional Neural Networks (GCNNs) in conjunction with an unsupervised graph clustering technique to result in the first tool, to our knowledge, to entirely automate this clustering process. We compare our algorithm to prior work in this space utilizing the four important figures of merit, and our results show over 90% accuracy across six different analog circuits, ranging in size and complexity, while taking just under 1 second to complete. Download Paper (PDF; Only available from the DATE venue WiFi)
16:45	12.6.4	EVPS: AN AUTOMOTIVE VIDEO ACQUISITION AND PROCESSING PLATFORM Speaker: Christophe Flouzat, CEA LIST, FR Authors: Christophe Flouzat1, Erwan Piriou2, Mickael Guibert1, Bojan Jovanovic1 and Mohamad Oussayran1 1CEA LIST, FR; 2CEA List, FR Abstract This paper describes a versatile and flexible video acquisition and processing platform for automotive. It is designed to meet aggressive requirements in terms of bandwidth and latency when implementing ADAS functions. Based on a Xilinx Ultrascale+ FPGA device, a vision processing pipeline mixing software and hardware tasks is implemented on this platform. This setup is able to collect four automotive camera streams (MIPI CSI2) and process them in the loop before transmitting a more intelligible pre-processed/enhanced data. Download Paper (PDF; Only available from the DATE venue WiFi)
17:00	12.6.5	AN ON-BOARD ALGORITHM IMPLEMENTATION ON AN EMBEDDED GPU: A SPACE CASE STUDY Speaker: Ivan Rodriguez, UPC / BSC, ES Authors: Ivan Rodriguez1, Leonidas Kosmidis2, Olivier Notebaert3, Francisco J Cazorla2 and David Steenari4 1UPC / BSC, ES; 2BSC, ES; 3Airbus Defence and Space, FR; 4European Space Agency, NL Abstract On-board processing requirements of future space missions are constantly increasing, calling for new hardware than the traditional ones used in space. Embedded GPUs are an attractive candidate offering both high performance capabilities and low power consumption, but there are no complex industrial case studies from the space domain demonstrating these advantages. In this paper we present the GPU parallelisation of an on-board algorithm, as well as its performance on a promising embedded GPU COTS platform targeting critical systems. Download Paper (PDF; Only available from the DATE venue WiFi)
17:15	12.6.6	TLS-LEVEL SECURITY FOR LOW POWER INDUSTRIAL IOT NETWORK INFRASTRUCTURES Authors: Jochen Mades1, Gerd Ebelt1, Boris Janjic1, Frederik Lauer2, Carl Rheinländer2 and Norbert Wehn2 1KSB SE & Co. KGaA, DE; 2TU Kaiserslautern, DE Abstract The Industrial Internet of Things (IIoT) enables communication services between machinery and cloud to enhance industrial processes e.g. by collecting relevant process parameters or providing predictable maintenance. Since the data is often origin from critical infrastructures, the security of the data channel is the main challenge, and is often weakened due to limited compute power and energy availability of battery-powered sensor nodes. Lightweight alternatives to standard security protocols avoid computationally intensive algorithms, however, they do not provide the same level of trust as established standards such as Transport Layer Security (TLS). In this paper, we propose an IIoT network system that enables a secure end-to-end IP communication between ultra-low-power sensor nodes and cloud servers. It provides full TLS support to ensure perfect forward secrecy by using hardware accelerators to reduce the energy demand of the security algorithms. Our results show that the energy overhead of the TLS handshake can be significantly reduced to enable a secure IIoT infrastructure with a reasonable battery lifetime of the edge devices. Download Paper (PDF; Only available from the DATE venue WiFi)
17:30		End of session