Date: Thursday 12 March 2020
Time: 14:00 - 15:30
Location / Room: Amphithéâtre Jean Prouve

Chair:
Olivier Sentieys, University of Rennes, IRISA, INRIA, FR

Co-Chair:
Gabriela Nicolescu, Polytechnique Montréal, CA

Time	Label	Presentation Title Authors
14:00	11.1.1	SYSTEM-LEVEL EVALUATION OF CHIP-SCALE SILICON PHOTONIC NETWORKS FOR EMERGING DATA- INTENSIVE APPLICATIONS Speaker: Ayse Coskun, Boston University, US Authors: Aditya Narayan1, Yvain Thonnart2, Pascal Vivet2, Ajay Joshi1 and Ayse Coskun1 1Boston University, US; 2CEA-Leti, FR Abstract Emerging data-driven applications such as graph processing applications are characterized by their excessive memory footprint and abundant parallelism, resulting in high memory bandwidth demand. As the scale of datasets for applications are reaching orders of TBs, performance limitation due to bandwidth demands is a major concern. Traditional on-chip electrical networks fail to meet such high bandwidth demands due to increased energy-per-bit or physical limitations with pin counts. Silicon photonic networks have emerged as a promising alternative to electrical interconnects, owing to their high bandwidth and low energy-per-bit communication with negligible data-dependent power. Wide-scale adoption of silicon photonics at chip level, however, is hampered by their high sensitivity to process and thermal variations, high laser power due to losses along the network, and power consumption of the electrical- optical conversion. Device-level technological innovations to mitigate these issues are promising, yet they do not consider the system-level implications of the applications running on manycore systems with photonic networks. This work aims to bridge the gap between the system-level attributes of applications with the underlying architectural and device-level characteristics of silicon photonic networks to achieve energy-efficient computing. We particularly focus on graph applications, which involve unstructured yet abundant parallel memory accesses that stress the on-chip communication networks, and develop a cross-layer framework to evaluate 2.5D systems with silicon photonic networks. We demonstrate significant energy savings through system-level management using wavelength selection policies and further evaluate architectural design choices on 2.5D systems with photonic networks. Download Paper (PDF; Only available from the DATE venue WiFi)
14:30	11.1.2	OSCAR: AN OPTICAL STOCHASTIC COMPUTING ACCELERATOR FOR POLYNOMIAL FUNCTIONS Speaker: Sébastien Le Beux, Concordia University, CA Authors: Hassnaa El-Derhalli, Sébastien Le Beux and Sofiène Tahar, Concordia University, CA Abstract Approximate computing allows to trade-off design energy efficiency with computing accuracy. Stochastic computing is an approximate computing technique, where numbers are represented as probabilities using stochastic bit streams. The serial computation of the bit streams leads to reduced hardware complexity but induces high latency, which is the main limitation of the approach. Silicon photonics has the potential to overcome the processing latency drawback thanks to high-speed propagation of signals and large bandwidth. However, the implementation of stochastic computing architectures using integrated optics involves high static energy that calls for adaptable architectures able to meet application-specific requirements. In this paper, we propose a reconfigurable optical accelerator allowing online adaptation of computing accuracy and energy efficiency according to the application requirements. The architecture can be configured to execute i) 4th order function for high accuracy processing or ii) 2nd order function for high-energy efficiency purposes. Evaluations are carried out using image processing Gamma correction function. Compared to a static architecture for which accuracy is defined at design time, the proposed architecture leads to 36.8% energy overhead but increases the range of reachable accuracy by 65%. Download Paper (PDF; Only available from the DATE venue WiFi)
15:00	11.1.3	POPSTAR: A ROBUST MODULAR OPTICAL NOC ARCHITECTURE FOR CHIPLET-BASED 3D INTEGRATED SYSTEMS Speaker: Yvain Thonnart, CEA-Leti, FR Authors: Yvain Thonnart1, Stéphane Bernabe1, Jean Charbonnier1, César Fuget Totolero1, Pierre Tissier1, Benoit Charbonnier1, Stephane Malhouitre1, Damien Saint-Patrice1, Myriam Assous1, Aditya Narayan2, Ayse Coskun2, Denis Dutoit1 and Pascal Vivet1 1CEA-Leti, FR; 2Boston University, US Abstract Silicon photonics technology is now gaining maturity with increasing levels of design complexity from devices to large photonic integrated circuits. Close integration of control electronics with 3D assembly of photonics and CMOS open the way to high-performance computing architectures partitioned in chiplets connected by optical NoC on silicon photonic interposers. In this paper, we give an overview of our works on optical links and NoC for manycore systems, from low-level control of photonic devices to high-level system optimization of the optical communications. We detail the POPSTAR architecture (Processors On Photonic Silicon interposer Terascale ARchitecture) with electro-optical interface chiplets, the corresponding nested spiral topology for single-writer multiple-reader links and the associated control electronics, in charge of high-speed drivers, thermal stabilization and handling of the protocol stack, from data integrity to flow-control, routing and arbitration of the optical communications. The strengths and opportunities for this architecture will be discussed, with a shift in system & implementation constraints with respect to previous optical NoC proposals, and new challenges to be addressed. Download Paper (PDF; Only available from the DATE venue WiFi)
15:30		End of session