Date: Tuesday 28 March 2017
Time: 17:00 - 18:30
Location / Room: 3C

Organiser:
Donatella Sciuto, Politecnico di Milano, IT

Chair:
Donatella Sciuto, Politecnico di Milano, IT

Co-Chair:
José L. Ayala, Universidad Complutense de Madrid, ES

The growing race towards exascale computing is pushing the adoption of ever more heterogeneous systems into mainstream. The resources available on a chip, the level of integration and the speed of components have increased dramatically over the years. Moreover, To handle the stringent performance requirements of future exascale-class applications, High Performance Computing (HPC) systems need ultra-efficient heterogeneous compute nodes. However, we keep on adopting superseded approaches to the exploitation of these resources. In this session, the speakers will focus on this requirements providing insight on how to enable the definition and the efficient deployment of such a technology.

Time	Label	Presentation Title Authors
17:00	4.5.1	TOWARDS EXASCALE COMPUTING WITH HETEROGENEOUS ARCHITECTURES Speaker: Kenneth O’Brien, Xilinx Inc., IE Authors: Kenneth O’Brien1, Lorenzo Di Tucci2, Gianluca Durelli1 and Michaela Blott1 1Xilinx, IE; 2Politecnico di Milano, IT Abstract The goal of reaching exascale computing is made especially challenging by the highly heterogeneous nature of modern platforms and the energy they consume. As compute nodes typically utilize multiple multi-core CPU and are increasingly equipped with PCIe based accelerators, both are contributing to an ever more dynamic power consumption. In our study we evaluate our target application on a variety of heterogeneous platforms, including high end FPGA, GPU, and Xeon Phi accelerators, with respect to energy efficiency at a node and cluster level. We compare multiple implementations of our application, each built with a different modern parallel programming framework, with respect to execution performance, code complexity and energy efficiency. Later we extrapolate based on our findings, the implications of scaling this application towards exascale, with projections of computation achievable within the exascale power budget for our three architectures. Download Paper (PDF; Only available from the DATE venue WiFi)
17:18	4.5.2	FROM EXAFLOP TO EXAFLOW Speaker: Tobias Becker, Maxeler Technologies, GB Authors: Tobias Becker1, Pavel Burovskiy2, Anna Maria Nestorov3, Hristina Palikareva2, Enrico Reggiani3 and Georgi Gaydadjiev4 1Maxeler Technologies, GB; 2Maxeler Technologies Ltd, GB; 3Politecnico di Milano, IT; 4Maxeler / Imperial College, GB Abstract Exascale computing is facing a gap between the ever increasing demand for application performance and the underlying chip technology that does no longer deliver the expected exponential increases in CPU performance. The industry is now progressively moving towards dedicated accelerators to deliver high performance and better energy efficiency. However, the question of programmability still remains. To address this challenge we propose a dedicated high-level accelerator programming and execution model where performance and efficiency are primary targets. Our model splits the computation into a conventional CPU-oriented part and a highly efficient fully programmable data flow part. We present a number of systematic transformations and optimisations targeting Maxeler dataflow systems that typically yield one to two orders of magnitude improvements in terms of both performance and energy efficiency. These significant gains are enabled by addressing fundamental algorithmic properties and on-demand numerical requirements. This approach is demonstrated by a case study from computational finance. Download Paper (PDF; Only available from the DATE venue WiFi)
17:36	4.5.3	HETEROGENEOUS EXASCALE SUPERCOMPUTING: THE ROLE OF CAD IN THE EXAFPGA PROJECT Speaker: Marco Santambrogio, Politecnico di Milano, IT Authors: Marco Rabozzi, Giuseppe Natale, Emanuele Del Sozzo, Alberto Scolari, Marco D. Santambrogio and Luca Stornaiuolo, Politecnico di Milano, IT Abstract Since the end of Moore's law is limiting the growth of general purpose processors, High Performance Processing (HPC) systems are considering FPGA-based accelerators as a promising solution for several application fields. However, their employment poses challenges the research is still tackling, and existing tools and workflows do not naturally adapt to the scale and complexity of HPC domains. To help researchers and practitioners, this paper proposes CAOS, a platform that implements an FPGA development workflow tailored to HPC systems while being open to external contributions. Indeed, researchers and developers can plug into CAOS to experiment and compare their solutions at each step of the design flow. This paper describes the CAOS workflow and validates it against several case studies to assess its generality and highlight possible research contributions. Download Paper (PDF; Only available from the DATE venue WiFi)
17:54	4.5.4	AN OPEN RECONFIGURABLE RESEARCH PLATFORM AS STEPPING STONE TO EXASCALE HIGH-PERFORMANCE COMPUTING Speaker: Dirk Stroobandt, Ghent University, BE Authors: Dirk Stroobandt1, Catalin Bogdan Ciobanu2, Marco D. Santambrogio3, Jose Gabriel Coutinho4, Andreas Brokalakis5, Dionisios Pnevmatikatos6, Michael Huebner7, Tobias Becker8 and Alex J. W. Thom9 1Ghent University, BE; 2UvA, NL; 3Politecnico di Milano, IT; 4Imperial College London, GB; 5Synelixis, GR; 6ECE Department, Technical Univrsity of Crete & FORTH-ICS, GR; 7Ruhr-University Bochum, DE; 8Maxeler Technologies, GB; 9University of Cambridge, GB Abstract To handle the stringent performance and power requirements of future exascale-class applications, High Performance Computing (HPC) systems need ultra-efficient heterogeneous compute nodes and hardware accelerators with a high degree of specialization. Ideally, dynamic reconfiguration will be an intrinsic feature, so that specific HPC application features can be optimally accelerated, even if they regularly change over time. We create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in as a core fundamental feature instead of an add-on. Our project proposes an open research platform that covers the entire stack from architecture up to the application, focusing on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new chip architectures with very low reconfiguration overhead, new tools that truly take reconfiguration as a central design concept, and applications that are tuned to maximally benefit from the proposed run-time reconfiguration techniques. Ultimately, this open platform will enable groundbreaking research towards new exascale computing platforms. Download Paper (PDF; Only available from the DATE venue WiFi)
18:12	4.5.5	GEOPM: A VEHICLE FOR EXASCALE COMMUNITY COLLABORATION TOWARD CO-DESIGNED ENERGY MANAGEMENT SOLUTIONS Speaker: Matthias Maiterth, Intel, US Author: Jonathan Eastep, Intel, US Abstract The power scaling challenge associated with Exascale systems is a well-known issue. In this invited talk, we provide an overview of the Global Extensible Open Power Manager (GEOPM). GEOPM is an open source power management runtime framework which is being contributed to the HPC community to foster collaboration on new power management runtime techniques to address Exascale power challenges or enhance performance and power efficiency on today's systems as well. Through GEOPM's plug-in extensible architecture, it enables rapid prototyping of new runtime algorithms. This talk will cover GEOPM's architecture, interfaces, and project status. For additional information, please visit: https://geopm.github.io/geopm/
18:30		End of session Exhibition Reception in Exhibition Area The Exhibition Reception will take place on Tuesday in the exhibition area, where free drinks for all conference delegates and exhibition visitors will be offered. All exhibitors are welcome to also provide drinks and snacks for the attendees.