2.6 Advancing Test for Mixed-Signal and Microfluidic Circuits and Systems

Time	Label	Presentation Title Authors
11:30	2.6.1	(Best Paper Award Candidate) ON THE LIMITS OF MACHINE LEARNING-BASED TEST: A CALIBRATED MIXED-SIGNAL SYSTEM CASE STUDY Speaker: Gildas Leger, Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES Authors: Manuel Barragan¹, Gildas Leger², Antonio Gines³, Eduardo Peralias⁴ and Adoracion Rueda³ ¹TIMA Laboratory, FR; ²Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES; ³Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC-Universidad de Sevilla), ES; ⁴Instituto de Microelectronica de Sevilla, IMSE-CNM, (CISC-Universidad de Sevilla), ES Abstract Testing analog, mixed-signal and RF circuits represents the main cost component for testing complex SoCs. A promising solution to alleviate this cost is the machine learning-based test strategy. These test techniques are an indirect test approach that replaces costly specification measurements by simpler signatures. Machine learning algorithms are used to map these signatures to the performance parameters. Although this approach has a number of undoubtable advantages, it also opens new issues that have to be addressed before it can be widely adopted by the industry. In this paper we present a machine learning-based test for a complex mixed-signal system -i.e. a state-of-the-art pipeline ADC- that includes digital calibration. This paper shows how the introduction of digital calibration for the ADC has a serious impact in the proposed test as calibration completely decorrelates signatures from the target specification in the presence of local mismatch. Download Paper (PDF; Only available from the DATE venue WiFi)
12:00	2.6.2	AN EXTENSION OF CROHN'S SENSITIVITY THEOREM TO MISMATCH ANALYSIS OF 1-PORT RESISTOR NETWORKS Speaker and Author: Sebastien Cliquennois, STMicroelectronics, FR Abstract An analytical expression of statistical mismatch properties of 1-port resistor networks and associated figure-of-merit is proposed, and related to Cohn's sensitivity theorem. This expression is then used to demonstrate matching properties of R-ladders. Experimental verification of this formula is done by comparing theoretical results to Monte-Carlo simulations of random R-networks up to 10 resistors, which are generated by a new graph-based algorithm. Further analysis is performed on this figure-of-merit for all generated networks, leading to more insights into matching properties of R-networks. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30	2.6.3	TESTING MICROFLUIDIC FULLY PROGRAMMABLE VALVE ARRAYS (FPVAS) Speaker: Chunfeng Liu, Technical University of Munich, DE Authors: Chunfeng Liu¹, Bing Li², Bhargab B. Bhattacharya³, Krishnendu Chakrabarty⁴, Tsung-Yi Ho⁵ and Ulf Schlichtmann⁶ ¹Technical University of Munich (TUM), DE; ²TU München (TUM), DE; ³Indian Statistical Institute, IN; ⁴Duke University, US; ⁵National Tsing Hua University, TW; ⁶TU München, DE Abstract Fully Programmable Valve Array (FPVA) has emerged as a new architecture for the next-generation flow-based microfluidic biochips. This 2D-array consists of regularly-arranged valves, which can be dynamically configured by users to realize microfluidic devices of different shapes and sizes as well as interconnections. Additionally, the regularity of the underlying structure renders FPVAs easier to integrate on a tiny chip. However, these arrays may suffer from various manufacturing defects such as blockage and leakage in control and flow channels. Unfortunately, no efficient method is yet known for testing such a general-purpose architecture. In this paper, we present a novel formulation using the concept of flow paths and cut-sets, and describe an ILP-based hierarchical strategy for generating compact test sets that can detect multiple faults in FPVAs. Simulation results demonstrate the efficacy of the proposed method in detecting manufacturing faults with only a small number of test vectors. Download Paper (PDF; Only available from the DATE venue WiFi)
13:00	IP1-6, 228	ANALOG FAULT TESTING THROUGH ABSTRACTION Speaker: Enrico Fraccaroli, Università degli Studi di Verona, IT Authors: Enrico Fraccaroli and Franco Fummi, Università degli Studi di Verona, IT Abstract Despite analog SPICE-like simulators have reached their maturity, most of them were not originally conceived for simulating faulty circuits. With the advent of smart systems, fault testing has to deal with models encompassing both analog and digital blocks. Due to their complexity, the industry is still lacking of effective testing approaches for these analog and mixed-signal (AMS) models. The current problem is the computational time required for implementing an analog fault simulation campaign. To this end, the work presented in this paper is an automatic procedure which: 1) injects faults in an analog circuit, 2) abstracts both faulty and fault-free models from the circuit to the functional level, 3) builds an efficient fault simulation framework. The processes of fault injection, faulty model abstraction and framework generation are reported in details, as well as how simulation is carried out. This abstraction process, which preserves the faulty behaviors, allows to reach a speed-up of some orders of magnitude and thus, making feasible an extensive analog faults campaign. Download Paper (PDF; Only available from the DATE venue WiFi)
13:01	IP1-7, 65	BISCC: EFFICIENT PRE THROUGH POST SILICON VALIDATION OF MIXED-SIGNAL/RF SYSTEMS USING BUILT IN STATE CONSISTENCY CHECKING Speaker: Abhijit Chatterjee, Georgia Institute of Technology, US Authors: Sabyasachi Deyati¹, Barry Muldrey¹ and Abhijit Chatterjee² ¹Georgia Institute of Technology, US; ²Georgia Tech, US Abstract High levels of integration in SoCs and SoPs is making pre as well as post-silicon validation of mixed-signal systems increasingly difficult due to: (a) lack of automated pre and post-silicon design checking algorithms and (b) lack of controllability and observability of internal circuit nodes in post-silicon. While digital scan chains provide observability of internal digital circuit states, analog scan chains suffer from signal integrity, bandwidth and circuit loading issues. In this paper, we propose a novel technique based on built-in state consistency checking that allows both pre as well as post-silicon validation of mixed-signal/RF systems without the need to rely on manually generated checks. The method is supported by a design-for-validation (DfV) methodology which systematically inserts a minimum amount of circuitry into mixed-signal systems for design bug detection and diagnosis purposes. The core idea is to apply two spectrally diverse stimuli to the circuit under test (CUT) in such a way that they result in the same circuit state (observed voltage/current values at internal or external circuit nodes). By comparing the resulting state values, design bugs are detected efficiently without the need for manually generated checks. No assumption is made about the nature of the detected bugs; the stimulus applied is steered towards those that are the most likely to detect design bugs. Test cases for both pre and post-silicon design bug detection and diagnosis prove the viability of the proposed BISCC approach. Download Paper (PDF; Only available from the DATE venue WiFi)
13:00		End of session Lunch Break in Garden Foyer Keynote Lecture session 3.0 in "Garden Foyer" 1350 - 1420 Lunch Break in the Garden Foyer On all conference days (Tuesday to Thursday), a buffet lunch will be offered in the Garden Foyer, in front of the session rooms. Kindly note that this is restricted to conference delegates possessing a lunch voucher only. When entering the lunch break area, delegates will be asked to present the corresponding lunch voucher of the day. Once the lunch area is being left, re-entrance is not allowed for the respective lunch.

Time

Label

Presentation Title
Authors

11:30

2.6.1

(Best Paper Award Candidate)
ON THE LIMITS OF MACHINE LEARNING-BASED TEST: A CALIBRATED MIXED-SIGNAL SYSTEM CASE STUDY
Speaker:
Gildas Leger, Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES
Authors:
Manuel Barragan¹, Gildas Leger², Antonio Gines³, Eduardo Peralias⁴ and Adoracion Rueda³
¹TIMA Laboratory, FR; ²Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES; ³Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC-Universidad de Sevilla), ES; ⁴Instituto de Microelectronica de Sevilla, IMSE-CNM, (CISC-Universidad de Sevilla), ES
Abstract
Testing analog, mixed-signal and RF circuits represents the main cost component for testing complex SoCs. A promising solution to alleviate this cost is the machine learning-based test strategy. These test techniques are an indirect test approach that replaces costly specification measurements by simpler signatures. Machine learning algorithms are used to map these signatures to the performance parameters. Although this approach has a number of undoubtable advantages, it also opens new issues that have to be addressed before it can be widely adopted by the industry. In this paper we present a machine learning-based test for a complex mixed-signal system -i.e. a state-of-the-art pipeline ADC- that includes digital calibration. This paper shows how the introduction of digital calibration for the ADC has a serious impact in the proposed test as calibration completely decorrelates signatures from the target specification in the presence of local mismatch.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:00

2.6.2

AN EXTENSION OF CROHN'S SENSITIVITY THEOREM TO MISMATCH ANALYSIS OF 1-PORT RESISTOR NETWORKS
Speaker and Author:
Sebastien Cliquennois, STMicroelectronics, FR
Abstract
An analytical expression of statistical mismatch properties of 1-port resistor networks and associated figure-of-merit is proposed, and related to Cohn's sensitivity theorem. This expression is then used to demonstrate matching properties of R-ladders. Experimental verification of this formula is done by comparing theoretical results to Monte-Carlo simulations of random R-networks up to 10 resistors, which are generated by a new graph-based algorithm. Further analysis is performed on this figure-of-merit for all generated networks, leading to more insights into matching properties of R-networks.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:30

2.6.3

TESTING MICROFLUIDIC FULLY PROGRAMMABLE VALVE ARRAYS (FPVAS)
Speaker:
Chunfeng Liu, Technical University of Munich, DE
Authors:
Chunfeng Liu¹, Bing Li², Bhargab B. Bhattacharya³, Krishnendu Chakrabarty⁴, Tsung-Yi Ho⁵ and Ulf Schlichtmann⁶
¹Technical University of Munich (TUM), DE; ²TU München (TUM), DE; ³Indian Statistical Institute, IN; ⁴Duke University, US; ⁵National Tsing Hua University, TW; ⁶TU München, DE
Abstract
Fully Programmable Valve Array (FPVA) has emerged as a new architecture for the next-generation flow-based microfluidic biochips. This 2D-array consists of regularly-arranged valves, which can be dynamically configured by users to realize microfluidic devices of different shapes and sizes as well as interconnections. Additionally, the regularity of the underlying structure renders FPVAs easier to integrate on a tiny chip. However, these arrays may suffer from various manufacturing defects such as blockage and leakage in control and flow channels. Unfortunately, no efficient method is yet known for testing such a general-purpose architecture. In this paper, we present a novel formulation using the concept of flow paths and cut-sets, and describe an ILP-based hierarchical strategy for generating compact test sets that can detect multiple faults in FPVAs. Simulation results demonstrate the efficacy of the proposed method in detecting manufacturing faults with only a small number of test vectors.
Download Paper (PDF; Only available from the DATE venue WiFi)

13:00

IP1-6, 228

ANALOG FAULT TESTING THROUGH ABSTRACTION
Speaker:
Enrico Fraccaroli, Università degli Studi di Verona, IT
Authors:
Enrico Fraccaroli and Franco Fummi, Università degli Studi di Verona, IT
Abstract
Despite analog SPICE-like simulators have reached their maturity, most of them were not originally conceived for simulating faulty circuits. With the advent of smart systems, fault testing has to deal with models encompassing both analog and digital blocks. Due to their complexity, the industry is still lacking of effective testing approaches for these analog and mixed-signal (AMS) models. The current problem is the computational time required for implementing an analog fault simulation campaign. To this end, the work presented in this paper is an automatic procedure which: 1) injects faults in an analog circuit, 2) abstracts both faulty and fault-free models from the circuit to the functional level, 3) builds an efficient fault simulation framework. The processes of fault injection, faulty model abstraction and framework generation are reported in details, as well as how simulation is carried out. This abstraction process, which preserves the faulty behaviors, allows to reach a speed-up of some orders of magnitude and thus, making feasible an extensive analog faults campaign.
Download Paper (PDF; Only available from the DATE venue WiFi)

13:01

IP1-7, 65

BISCC: EFFICIENT PRE THROUGH POST SILICON VALIDATION OF MIXED-SIGNAL/RF SYSTEMS USING BUILT IN STATE CONSISTENCY CHECKING
Speaker:
Abhijit Chatterjee, Georgia Institute of Technology, US
Authors:
Sabyasachi Deyati¹, Barry Muldrey¹ and Abhijit Chatterjee²
¹Georgia Institute of Technology, US; ²Georgia Tech, US
Abstract
High levels of integration in SoCs and SoPs is making pre as well as post-silicon validation of mixed-signal systems increasingly difficult due to: (a) lack of automated pre and post-silicon design checking algorithms and (b) lack of controllability and observability of internal circuit nodes in post-silicon. While digital scan chains provide observability of internal digital circuit states, analog scan chains suffer from signal integrity, bandwidth and circuit loading issues. In this paper, we propose a novel technique based on built-in state consistency checking that allows both pre as well as post-silicon validation of mixed-signal/RF systems without the need to rely on manually generated checks. The method is supported by a design-for-validation (DfV) methodology which systematically inserts a minimum amount of circuitry into mixed-signal systems for design bug detection and diagnosis purposes. The core idea is to apply two spectrally diverse stimuli to the circuit under test (CUT) in such a way that they result in the same circuit state (observed voltage/current values at internal or external circuit nodes). By comparing the resulting state values, design bugs are detected efficiently without the need for manually generated checks. No assumption is made about the nature of the detected bugs; the stimulus applied is steered towards those that are the most likely to detect design bugs. Test cases for both pre and post-silicon design bug detection and diagnosis prove the viability of the proposed BISCC approach.
Download Paper (PDF; Only available from the DATE venue WiFi)

13:00

End of session
Lunch Break in Garden Foyer

Keynote Lecture session 3.0 in "Garden Foyer" 1350 - 1420

Lunch Break in the Garden Foyer
On all conference days (Tuesday to Thursday), a buffet lunch will be offered in the Garden Foyer, in front of the session rooms. Kindly note that this is restricted to conference delegates possessing a lunch voucher only. When entering the lunch break area, delegates will be asked to present the corresponding lunch voucher of the day. Once the lunch area is being left, re-entrance is not allowed for the respective lunch.