Date: Wednesday 16 March 2016
Time: 17:00 - 18:30
Location / Room: Konferenz 5
Chair:
Friedrich Hapke, Mentor Graphics Hamburg, DE
Improving the quality of the test and analysis process is crucial from a technical and economical point of view. Novel methods are presented to improve ATPG in the presence of unkowns, to allow pre-bond interposer testing and to exploit the memory infrastructure to improve defect coverage. The session is complemented by an ATPG approach based on behavioral fault models, a hierarchrchical DFT methodology, and a safety analysis process combining simulation-based fault injection with graph-based guidance.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 17:00 | 8.7.1 | ACCURATE CEGAR-BASED ATPG IN PRESENCE OF UNKNOWN VALUES FOR LARGE INDUSTRIAL DESIGNS Speaker: Karsten Scheibler, University of Freiburg, DE Authors: Karsten Scheibler, Dominik Erb and Bernd Becker, University of Freiburg, DE Abstract Unknown values emerge during the design and test generation process as well as during later test application and system operation. They adversely affect the test quality by reducing the controllability and observability of internal circuit structures -- resulting in a loss of fault coverage. To handle unknown values, conventional test generation algorithms as used in state-of-the-art commercial tools, rely on n-valued algebras. However, n-valued algebras introduce pessimism as soon as X-values reconverge. Consequently, these algorithms fail to compute the accurate result. Therefore, this paper focuses on a new highly incremental CEGAR-based algorithm that overcomes these limitations and hence is completely accurate in presence of unknown values. It relies on a modified SAT-solver tailored to this specific problem. The experimental results for circuits with up to 2.400.000 gates show that this combination allows high accuracy and high scalability at the same time. Compared to a state-of-the-art commercial tool, the fault coverage could be increased significantly. Furthermore, the runtime is reduced remarkably compared to a QBF-based encoding of the problem. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:30 | 8.7.2 | (Best Paper Award Candidate) PRE-BOND TESTING OF THE SILICON INTERPOSER IN 2.5D ICS Speaker: Ran Wang, Duke University, US Authors: Ran Wang1, Zipeng Li1, Sukeshwar Kannan2 and Krishnendu Chakrabarty1 1Duke University, US; 2Global Foundries Inc., US Abstract In interposer-based 2.5D integrated circuits, the silicon interposer is the least expensive component in the chip. Thus, it is desirable to test the interposer before bonding to ensure that more expensive and defect-free dies are not stacked on a faulty interposer. We present an efficient method to locate defects in the interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. In order to reduce test time, the concept of weighted critical area is defined and utilized.We present HSPICE simulation results to demonstrate the effectiveness of the pre-bond test solution. The benefit of using weighted critical area is demonstrated using a commercial interposer from industry. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:00 | 8.7.3 | IMPROVING SRAM TEST QUALITY BY LEVERAGING SELF-TIMED CIRCUITS Speaker: Josef Kinseher, Intel Mobile Communications, DE Authors: Josef Kinseher1, Leonardo B. Zordan2, Ilia Polian3 and Andreas Leininger1 1Intel Mobile Communications, DE; 2Intel Mobile Communications, FR; 3University of Passau, DE Abstract As process technology continues to scale, SRAM test quality has become a growing concern in modern System-on- a-Chips. Ensuring high test quality while keeping costs low requires increasingly effective memory test solutions. This paper proposes the reuse of self-timing mechanisms that are integrated in many state-of-the-art SRAMs as a programmable DFT solution to improve the defect coverage of memory test algorithms. Its effectiveness is analyzed based on the injection of resistive-open defects inside SRAM core-cells. Simulation results of an industrial 28nm memory design show that the proposed test solution increases the coverage of studied defects by up to 30% dependent on their location, while not requiring extra circuitry inside the SRAM. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | IP4-4, 260 | A SYNTHESIS-AGNOSTIC BEHAVIORAL FAULT MODEL FOR HIGH GATE-LEVEL FAULT COVERAGE Speaker: Anton Karputkin, Tallinn University of Technology, EE Authors: Anton Karputkin and Jaan Raik, Tallinn University of Technology, EE Abstract Early design space exploration is a practice for avoiding issues that manifest themselves at late design phases. Nevertheless, the test development has traditionally been postponed to the final stages of the design process. At the same time, more and more IP designs are sold at the RTL, where details of exact gate-level implementation are unknown. While a range of RTL ATPG methods has been developed over the past decades, the fault models are too inaccurate in order to guarantee full coverage for the gate-level faults. This paper fills the gap by proposing a synthesis-agnostic ATPG based on extending behavioral fault models in order to allow targeting stuck-at faults in the gate-level implementations of RTL designs regardless of the synthesis decisions made. Moreover, the approach does not require adding scan paths and therefore the obtained test sequences serve as at-speed, functional mode tests. Experiments on a set of benchmarks and an industrial design show that the proposed fault models are superior to the previous approaches in terms of stuck-at fault coverage. Comparison with a state-of-the-art gate-level sequential ATPG show higher or equal coverage for the proposed technique achieved at shorter runtimes. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:32 | IP4-6, 672 | (Best Paper Award Candidate) COMBINING GRAPH-BASED GUIDANCE AND ERROR EFFECT SIMULATION FOR EFFICIENT SAFETY ANALYSIS Speaker: Jo Laufenberg, Universität Tübingen, DE Authors: Jo Laufenberg1, Sebastian Reiter2, Alexander Viehl2, Thomas Kropf1, Wolfgang Rosenstiel1 and Oliver Bringmann1 1Universität Tübingen, DE; 2FZI Forschungszentrum Informatik, DE Abstract The increasing number of complex embedded systems used in safety relevant tasks produce a major challenge in the field of safety analysis. This paper presents a simulation-based safety analysis that will overcome the challenges resulting from this development. The presented approach consists of two parts: an Error Effect Simulation (EES) and a graph-based specification. The EES is composed of a system simulation with fault injection capability and a generic fault specification. The graph-based specification approach guides systematically the EES and enables a very efficient exploration of the analysis space. Inherent in the graph-based specification is the documentation of the safety analysis and a coverage approach to assess the executed safety analysis. Combining these parts leads to an efficient and automatable framework for safety analysis. A use case of an interconnected electronic control system shows the application of the approach and highlights the benefits for a safety analysis, for example a failure mode and effect analysis. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | End of session | |