IP4 Interactive Presentations

Label	Presentation Title Authors
IP4-1	A Q-GRAM BIRTHMARKING APPROACH TO PREDICTING REUSABLE HARDWARE Speaker: Kevin Zeng, Virginia Tech, US Authors: Kevin Zeng and Peter Athanas, Virginia Tech, US Abstract Designer productivity is a growing concern as overall hardware complexity rises. Design reuse, a key component in productivity, is underutilized. Not only can existing designs be reused, but also the patterns and information contained within them as well. With the increase in the number of circuits available, there requires a need to analyze and retrieve designs with ease in order to accelerate design entry. In this paper, a birthmarking approach using q-grams is presented. Using this technique, design patterns regarding existing circuits can be captured and used to not only suggest similar and reusable designs, but functional blocks throughout the design phase, with little to no effort from the user. Preliminary experiments and case studies of the q-gram birthmarking technique were performed on over 250 circuits from various sources in order to show the feasibility of the proposed methods. Download Paper (PDF; Only available from the DATE venue WiFi)
IP4-2	CAPTOPRIL: REDUCING THE PRESSURE OF BIT FLIPS ON HOT LOCATIONS IN NON-VOLATILE MAIN MEMORIES Speaker: Majid Jalili, Sharif University of Technology, IR Authors: Majid Jalili and Hamid Sarbazi-Azad, Sharif University of Technology, IR Abstract High static power consumption and insufficient scalability of the commonly used DRAM main memory technology appear to be tough challenges in upcoming years. Hence, adopting new technologies, i.e. non-volatile memories (NVMs), is a proper choice. NVMs tolerate a low number of write operations while having good scalability and low static power consumption. Due to the non-destructive nature of a read operation and the long latency of a write operation in NVMs, designers use read-before-write (RBW) mechanism to mask the unchanged bits during write operation in order to reduce bit flips. Based on this observation that some specific locations of blocks are responsible for the majority of bit flips, we extend the RBW to further reduce the number of bit flips per write in the memory system. The results taken from full-system simulations reveal that our proposal, called Captopril, can reduce the number of bit flips by 21% and 9%, on average, compared to the baseline and state-of-the-art designs, respectively Download Paper (PDF; Only available from the DATE venue WiFi)
IP4-3	HANDLING COMPLEX DEPENDENCIES IN SYSTEM DESIGN Speaker: Mischa Möstl, Technische Universität Braunschweig, DE Authors: Mischa Möstl and Rolf Ernst, Technische Universität Braunschweig, DE Abstract In this paper we describe a novel strategy to reveal and handle complex dependencies in an incremental and distributed design processes even under the ubiquitous presence of uncertainties concerning model and design. We demonstrate in a case study how to handle epistemic design uncertainty in an iterative process and present how it is possible to selectively exclude dependency paths under certain concerns such as timing by including third party analysis results based on the used models into the dependency analysis. Since the implementation of our approach relies on modern graph analysis libraries it can scale to realistic problem instances. Download Paper (PDF; Only available from the DATE venue WiFi)
IP4-4	A SYNTHESIS-AGNOSTIC BEHAVIORAL FAULT MODEL FOR HIGH GATE-LEVEL FAULT COVERAGE Speaker: Anton Karputkin, Tallinn University of Technology, EE Authors: Anton Karputkin and Jaan Raik, Tallinn University of Technology, EE Abstract Early design space exploration is a practice for avoiding issues that manifest themselves at late design phases. Nevertheless, the test development has traditionally been postponed to the final stages of the design process. At the same time, more and more IP designs are sold at the RTL, where details of exact gate-level implementation are unknown. While a range of RTL ATPG methods has been developed over the past decades, the fault models are too inaccurate in order to guarantee full coverage for the gate-level faults. This paper fills the gap by proposing a synthesis-agnostic ATPG based on extending behavioral fault models in order to allow targeting stuck-at faults in the gate-level implementations of RTL designs regardless of the synthesis decisions made. Moreover, the approach does not require adding scan paths and therefore the obtained test sequences serve as at-speed, functional mode tests. Experiments on a set of benchmarks and an industrial design show that the proposed fault models are superior to the previous approaches in terms of stuck-at fault coverage. Comparison with a state-of-the-art gate-level sequential ATPG show higher or equal coverage for the proposed technique achieved at shorter runtimes. Download Paper (PDF; Only available from the DATE venue WiFi)
IP4-6	(Best Paper Award Candidate) COMBINING GRAPH-BASED GUIDANCE AND ERROR EFFECT SIMULATION FOR EFFICIENT SAFETY ANALYSIS Speaker: Jo Laufenberg, Universität Tübingen, DE Authors: Jo Laufenberg¹, Sebastian Reiter², Alexander Viehl², Thomas Kropf¹, Wolfgang Rosenstiel¹ and Oliver Bringmann¹ ¹Universität Tübingen, DE; ²FZI Forschungszentrum Informatik, DE Abstract The increasing number of complex embedded systems used in safety relevant tasks produce a major challenge in the field of safety analysis. This paper presents a simulation-based safety analysis that will overcome the challenges resulting from this development. The presented approach consists of two parts: an Error Effect Simulation (EES) and a graph-based specification. The EES is composed of a system simulation with fault injection capability and a generic fault specification. The graph-based specification approach guides systematically the EES and enables a very efficient exploration of the analysis space. Inherent in the graph-based specification is the documentation of the safety analysis and a coverage approach to assess the executed safety analysis. Combining these parts leads to an efficient and automatable framework for safety analysis. A use case of an interconnected electronic control system shows the application of the approach and highlights the benefits for a safety analysis, for example a failure mode and effect analysis. Download Paper (PDF; Only available from the DATE venue WiFi)
IP4-7	PACKET SECURITY WITH PATH SENSITIZATION FOR NOCS Speaker: Travis Boraten, Ohio University, US Authors: Travis Boraten and Avinash Kodi, Ohio University, US Abstract Hardware security is becoming a major concern as integrated circuits (IC) are exponentially growing thanks to technology scaling. With ICs reaching upwards of billions of transistors, detecting hardware trojans (HT) is like finding a needle in a haystack. Therefore, it becomes imperative to protect critical computing infrastructure from malicious attackers attempting to unearth vital information. Security enhancements should offer resiliency to limit their impact on overall chip performance as HTs are likely to slip through detection mechanisms. In this paper, we propose packet-security (P-Sec) a packet validation technique to protect compromised network-on-chip (NoC) architectures from fault injection side channel attacks and covert HT communication by merging two robust error detection schemes, namely algebraic manipulation detection (AMD) and cyclic redundancy check (CRC) codes. With P-Sec, applications containing sensitive and encrypted data can be protected from an ideal attacker using AMD codes at the cost of marginal area and power overhead in the network interface but with enhanced security on demand. Download Paper (PDF; Only available from the DATE venue WiFi)
IP4-8	SYNTHESIS OF APPROXIMATE CODERS FOR ON-CHIP INTERCONNECTS USING REVERSIBLE LOGIC Speaker: Robert Wille, Johannes Kepler University Linz, AT Authors: Robert Wille¹, Oliver Keszocze², Stefan Hillmich², Marcel Walter² and Alberto Garcia-Ortiz³ ¹Johannes Kepler University Linz, AT; ²University of Bremen, DE; ³ITEM (U.Bremen), DE Abstract On-chip coding provides a remarkable potential to improve the energy efficiency of on-chip interconnects. However, the logic design of the encoder/decoder faces a main challenge: the area and power overhead should be minimal while, at the same time, decodability has to be guaranteed. To address these problems, we propose the concept of approximate coding, where the coding function is partially specified and the synthesis algorithm has a higher flexibility to simplify the circuit. Since conventional synthesis methods are unsuitable here, we propose an alternative synthesis approach based on reversible logic. Experimental evaluations confirm the benefits of both, the proposed concept of approximate codings as well as the proposed design method. Download Paper (PDF; Only available from the DATE venue WiFi)
IP4-9	DESIGN-SYNTHESIS CO-OPTIMISATION USING SKEWED AND TAPERED GATES Speaker: Ankur Shukla, India Systems Development Lab, IBM India, IN Authors: Ayan Datta¹, James D. Warnock², Ankur Shukla¹, Saurabh Gupta¹, Yiu Hing Chan², Karthik Mohan¹ and Charudhattan Nagarajan¹ ¹India Systems Development Lab, IBM India, IN; ²IBM US, US Abstract This paper presents a novel technique to optimize the design of non-conventional tapered and skewed standard cell gates, and the synthesis algorithms for efficient usage of such gates in IBMs high-performance 22nm CMOS SOI technology. The focus is on design considerations to ensure that synthesis can use these gates efficiently, leveraging the resulting timing improvements for faster timing closure of high-performance microprocessor designs. A detailed analysis is presented, where by exposing these gates to synthesis at different points in the process, the optimal point of insertion is identified. Also an efficient algorithm is proposed to handle decisions regarding the conversion of conventional gates to non-conventional gates, after taking into account multiple factors including delay and slew. Results show 25 - 30% improvement in total negative slack of designs and 20 -25% reduction in the total number of negative paths, without any major impact on total power of the designs. Download Paper (PDF; Only available from the DATE venue WiFi)
IP4-10	(Best Paper Award Candidate) A SYNTHESIS-PARAMETER TUNING SYSTEM FOR AUTONOMOUS DESIGN-SPACE EXPLORATION Speaker: Matthew Ziegler, IBM T. J. Watson Research Center, US Authors: Matthew Ziegler¹, Hung-Yi Liu², George Gristede¹, Bruce Owens³, Ricardo Nigaglioni³ and Luca Carloni² ¹IBM T. J. Watson Research Center, US; ²Columbia University, US; ³IBM Systems and Technology Group, US Abstract Advanced logic and physical synthesis tools provide a vast num-ber of tunable parameters that can significantly impact physical design quality, but the complexity of the parameter design space requires intelligent search algorithms. To fully utilize the opti-mization potential of these tools, we propose SynTunSys, a sys-tem that adds a new level of abstraction between designers and design tools for managing the design space exploration process. SynTunSys takes control of the synthesis-parameter tuning pro-cess, i.e., job submission, results analysis, and next-step decision making, by automating a key portion of a human designer's decision process. We present the overall organization of Syn-TunSys, describe its main components, and provide results from employing it for the design of an industrial chip, the IBM z13 22nm high-performance server chip. During this major design, SynTunSys provided significant savings in human design effort and achieved a quality of results beyond what human designers alone could achieve, yielding on average a 36% improvement in total negative slack and a 7% power reduction. Download Paper (PDF; Only available from the DATE venue WiFi)
IP4-11	UNBOUNDED SAFETY VERIFICATION FOR HARDWARE USING SOFTWARE ANALYZERS Speaker: Rajdeep Mukherjee, University of Oxford, GB Authors: Rajdeep Mukherjee, Peter Schrammel, Daniel Kroening and Tom Melham, University of Oxford, GB Abstract Demand for scalable hardware verification is ever increasing. We propose an unbounded safety verification framework for hardware, at the heart of which is a software verifier. To this end, we synthesize Verilog at register transfer level into a software-netlist, represented as a word-level ANSI-C program. The proposed tool flow allows us to leverage the precision and scalability of state-of-the-art software verification techniques. In particular, we evaluate unbounded proof techniques, such as predicate abstraction, k-induction, interpolation, and IC3/PDR; and we compare the performance of verification tools from the hardware and software domains that use these techniques. To the best of our knowledge, this is the first attempt to perform unbounded verification of hardware using software analyzers. Download Paper (PDF; Only available from the DATE venue WiFi)
IP4-12	VERILOG2SMV: A TOOL FOR WORD-LEVEL VERIFICATION Speaker: Ahmed Irfan, Fondazione Bruno Kessler and University of Trento, IT Authors: Ahmed Irfan¹, Alessandro Cimatti², Alberto Griggio², Marco Roveri² and Roberto Sebastiani³ ¹Fondazione Bruno Kessler and University of Trento, IT; ²Fondazione Bruno Kessler, IT; ³University of Trento, IT Abstract Verification is an essential step of the hardware design lifecycle. Usually verification is done at the gate level (Boolean level). We present verilog2smv, a tool that generates word-level model checking problems from Verilog designs augmented with assertions. A key aspect of our tool is that memories in the designs are treated without any form of abstraction. verilog2smv can be used for RTL verification by chaining with a word-level model checker like nuXmv. To this extent, we present also some experimental results over Verilog verification benchmarks, using verilog2smv + nuXmv as a tool-chain. Download Paper (PDF; Only available from the DATE venue WiFi)
IP4-13	TOWARDS FORMAL VERIFICATION OF REAL-WORLD SYSTEMC TLM PERIPHERAL MODELS - A CASE STUDY Speaker: Vladimir Herdt, University of Bremen, DE Authors: Hoang M. Le¹, Vladimir Herdt¹, Daniel Grosse¹ and Rolf Drechsler² ¹University of Bremen, DE; ²University of Bremen and DFKI, DE Abstract SystemC-based Virtual Prototypes (VPs) serve as reference models for various activities in the modern design flow and therefore, the functional correctness of each individual components and the VPs as a whole should be subjected to rigorous formal verification. In the last few years, notable progress on SystemC formal verification has been made. This paper presents a case study on applying a recent approach to formally verify TLM peripheral models. To the best of our knowledge, this is the first formal verification case study targeting this important class of VP components. First, we show how to bridge the gap between the industry-accepted modeling pattern for TLM peripheral models and the semantics currently supported by SystemC formal verification approaches. Then, we report verification results for the interrupt controller of the LEON3-based SoCRocket VP used by the European Space Agency and reflect on our experiences and lessons learned in the process. Download Paper (PDF; Only available from the DATE venue WiFi)
IP4-14	FREQUENCY SCHEDULING FOR RESILIENT CHIP MULTI-PROCESSORS OPERATING AT NEAR THRESHOLD VOLTAGE Speaker: Huawei Li, Chinese Academy of Sciences, CN Authors: Ying Wang, Huawei Li and Xiaowei Li, Chinese Academy of Sciences, CN Abstract With the recently proposed redundancy-based core salvaging technology, resilient processors can survive the threat of severe timing violation induced by near-threshold Vdd and function correctly at aggressive clock rates. In our observation, proactively disabling the weakest components that limit the core frequency can still maintain a higher throughput at Near Threshold Voltage (NTV) supply if the cores with defected components are salvaged at a low cost. In this work, a resilience-aware frequency scaling and mapping strategy that considers defected processor states in scheduling is proposed to exploit the fault-tolerant architectures for higher energy efficiency. In our evaluation, it is witnessed that typical resilient multi-core processors can achieve significantly higher performance per watt in experiments compared to conventional scheduling policy. Download Paper (PDF; Only available from the DATE venue WiFi)
IP4-15	(Best Paper Award Candidate) A LOW OVERHEAD ERROR CONFINEMENT METHOD BASED ON APPLICATION STATISTICAL CHARACTERISTICS Speaker: Anupam Chattopadhyay, Nanyang Technological University, SG Authors: Zheng Wang¹, Georgios Karakonstantis² and Anupam Chattopadhyay³ ¹RWTH-Aachen University, DE; ²Queen's University, GB; ³Nanyang Technological University, SG Abstract Reliability has emerged as a critical design constraint especially in memories. Designers have spent great efforts to guarantee fault free operation of the underlying silicon by adopting redundancy-based techniques, which essentially try to detect and correct every single error. However, such techniques come at a cost of large area, power and performance overheads which make many to doubt their efficiency especially for error resilient systems where 100% accuracy is not always required. In this paper, we present an alternative method focusing on the confinement of the resulting output error induced by any reliability issues. By focusing on memory faults, rather than correcting every single error the proposed method exploits the statistical characteristics of any target application and replaces any erroneous data with the best available estimate of that data. To realize the proposed method a RISC processor is augmented with custom instructions and special-purpose functional units. We apply the method on the proposed enhanced processor by studying the statistical characteristics of the various algorithms involved in a popular multimedia application. Our experimental results show that in contrast to state-of-the-art fault tolerance approaches, we are able to reduce runtime and area overhead by 71.3% and 83.3% respectively. Download Paper (PDF; Only available from the DATE venue WiFi)

Label

Presentation Title
Authors

IP4-1

A Q-GRAM BIRTHMARKING APPROACH TO PREDICTING REUSABLE HARDWARE
Speaker:
Kevin Zeng, Virginia Tech, US
Authors:
Kevin Zeng and Peter Athanas, Virginia Tech, US
Abstract
Designer productivity is a growing concern as overall hardware complexity rises. Design reuse, a key component in productivity, is underutilized. Not only can existing designs be reused, but also the patterns and information contained within them as well. With the increase in the number of circuits available, there requires a need to analyze and retrieve designs with ease in order to accelerate design entry. In this paper, a birthmarking approach using q-grams is presented. Using this technique, design patterns regarding existing circuits can be captured and used to not only suggest similar and reusable designs, but functional blocks throughout the design phase, with little to no effort from the user. Preliminary experiments and case studies of the q-gram birthmarking technique were performed on over 250 circuits from various sources in order to show the feasibility of the proposed methods.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP4-2

CAPTOPRIL: REDUCING THE PRESSURE OF BIT FLIPS ON HOT LOCATIONS IN NON-VOLATILE MAIN MEMORIES
Speaker:
Majid Jalili, Sharif University of Technology, IR
Authors:
Majid Jalili and Hamid Sarbazi-Azad, Sharif University of Technology, IR
Abstract
High static power consumption and insufficient scalability of the commonly used DRAM main memory technology appear to be tough challenges in upcoming years. Hence, adopting new technologies, i.e. non-volatile memories (NVMs), is a proper choice. NVMs tolerate a low number of write operations while having good scalability and low static power consumption. Due to the non-destructive nature of a read operation and the long latency of a write operation in NVMs, designers use read-before-write (RBW) mechanism to mask the unchanged bits during write operation in order to reduce bit flips. Based on this observation that some specific locations of blocks are responsible for the majority of bit flips, we extend the RBW to further reduce the number of bit flips per write in the memory system. The results taken from full-system simulations reveal that our proposal, called Captopril, can reduce the number of bit flips by 21% and 9%, on average, compared to the baseline and state-of-the-art designs, respectively
Download Paper (PDF; Only available from the DATE venue WiFi)

IP4-3

HANDLING COMPLEX DEPENDENCIES IN SYSTEM DESIGN
Speaker:
Mischa Möstl, Technische Universität Braunschweig, DE
Authors:
Mischa Möstl and Rolf Ernst, Technische Universität Braunschweig, DE
Abstract
In this paper we describe a novel strategy to reveal and handle complex dependencies in an incremental and distributed design processes even under the ubiquitous presence of uncertainties concerning model and design. We demonstrate in a case study how to handle epistemic design uncertainty in an iterative process and present how it is possible to selectively exclude dependency paths under certain concerns such as timing by including third party analysis results based on the used models into the dependency analysis. Since the implementation of our approach relies on modern graph analysis libraries it can scale to realistic problem instances.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP4-4

A SYNTHESIS-AGNOSTIC BEHAVIORAL FAULT MODEL FOR HIGH GATE-LEVEL FAULT COVERAGE
Speaker:
Anton Karputkin, Tallinn University of Technology, EE
Authors:
Anton Karputkin and Jaan Raik, Tallinn University of Technology, EE
Abstract
Early design space exploration is a practice for avoiding issues that manifest themselves at late design phases. Nevertheless, the test development has traditionally been postponed to the final stages of the design process. At the same time, more and more IP designs are sold at the RTL, where details of exact gate-level implementation are unknown. While a range of RTL ATPG methods has been developed over the past decades, the fault models are too inaccurate in order to guarantee full coverage for the gate-level faults. This paper fills the gap by proposing a synthesis-agnostic ATPG based on extending behavioral fault models in order to allow targeting stuck-at faults in the gate-level implementations of RTL designs regardless of the synthesis decisions made. Moreover, the approach does not require adding scan paths and therefore the obtained test sequences serve as at-speed, functional mode tests. Experiments on a set of benchmarks and an industrial design show that the proposed fault models are superior to the previous approaches in terms of stuck-at fault coverage. Comparison with a state-of-the-art gate-level sequential ATPG show higher or equal coverage for the proposed technique achieved at shorter runtimes.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP4-6

(Best Paper Award Candidate)
COMBINING GRAPH-BASED GUIDANCE AND ERROR EFFECT SIMULATION FOR EFFICIENT SAFETY ANALYSIS
Speaker:
Jo Laufenberg, Universität Tübingen, DE
Authors:
Jo Laufenberg¹, Sebastian Reiter², Alexander Viehl², Thomas Kropf¹, Wolfgang Rosenstiel¹ and Oliver Bringmann¹
¹Universität Tübingen, DE; ²FZI Forschungszentrum Informatik, DE
Abstract
The increasing number of complex embedded systems used in safety relevant tasks produce a major challenge in the field of safety analysis. This paper presents a simulation-based safety analysis that will overcome the challenges resulting from this development. The presented approach consists of two parts: an Error Effect Simulation (EES) and a graph-based specification. The EES is composed of a system simulation with fault injection capability and a generic fault specification. The graph-based specification approach guides systematically the EES and enables a very efficient exploration of the analysis space. Inherent in the graph-based specification is the documentation of the safety analysis and a coverage approach to assess the executed safety analysis. Combining these parts leads to an efficient and automatable framework for safety analysis. A use case of an interconnected electronic control system shows the application of the approach and highlights the benefits for a safety analysis, for example a failure mode and effect analysis.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP4-7

PACKET SECURITY WITH PATH SENSITIZATION FOR NOCS
Speaker:
Travis Boraten, Ohio University, US
Authors:
Travis Boraten and Avinash Kodi, Ohio University, US
Abstract
Hardware security is becoming a major concern as integrated circuits (IC) are exponentially growing thanks to technology scaling. With ICs reaching upwards of billions of transistors, detecting hardware trojans (HT) is like finding a needle in a haystack. Therefore, it becomes imperative to protect critical computing infrastructure from malicious attackers attempting to unearth vital information. Security enhancements should offer resiliency to limit their impact on overall chip performance as HTs are likely to slip through detection mechanisms. In this paper, we propose packet-security (P-Sec) a packet validation technique to protect compromised network-on-chip (NoC) architectures from fault injection side channel attacks and covert HT communication by merging two robust error detection schemes, namely algebraic manipulation detection (AMD) and cyclic redundancy check (CRC) codes. With P-Sec, applications containing sensitive and encrypted data can be protected from an ideal attacker using AMD codes at the cost of marginal area and power overhead in the network interface but with enhanced security on demand.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP4-8

SYNTHESIS OF APPROXIMATE CODERS FOR ON-CHIP INTERCONNECTS USING REVERSIBLE LOGIC
Speaker:
Robert Wille, Johannes Kepler University Linz, AT
Authors:
Robert Wille¹, Oliver Keszocze², Stefan Hillmich², Marcel Walter² and Alberto Garcia-Ortiz³
¹Johannes Kepler University Linz, AT; ²University of Bremen, DE; ³ITEM (U.Bremen), DE
Abstract
On-chip coding provides a remarkable potential to improve the energy efficiency of on-chip interconnects. However, the logic design of the encoder/decoder faces a main challenge: the area and power overhead should be minimal while, at the same time, decodability has to be guaranteed. To address these problems, we propose the concept of approximate coding, where the coding function is partially specified and the synthesis algorithm has a higher flexibility to simplify the circuit. Since conventional synthesis methods are unsuitable here, we propose an alternative synthesis approach based on reversible logic. Experimental evaluations confirm the benefits of both, the proposed concept of approximate codings as well as the proposed design method.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP4-9

DESIGN-SYNTHESIS CO-OPTIMISATION USING SKEWED AND TAPERED GATES
Speaker:
Ankur Shukla, India Systems Development Lab, IBM India, IN
Authors:
Ayan Datta¹, James D. Warnock², Ankur Shukla¹, Saurabh Gupta¹, Yiu Hing Chan², Karthik Mohan¹ and Charudhattan Nagarajan¹
¹India Systems Development Lab, IBM India, IN; ²IBM US, US
Abstract
This paper presents a novel technique to optimize the design of non-conventional tapered and skewed standard cell gates, and the synthesis algorithms for efficient usage of such gates in IBMs high-performance 22nm CMOS SOI technology. The focus is on design considerations to ensure that synthesis can use these gates efficiently, leveraging the resulting timing improvements for faster timing closure of high-performance microprocessor designs. A detailed analysis is presented, where by exposing these gates to synthesis at different points in the process, the optimal point of insertion is identified. Also an efficient algorithm is proposed to handle decisions regarding the conversion of conventional gates to non-conventional gates, after taking into account multiple factors including delay and slew. Results show 25 - 30% improvement in total negative slack of designs and 20 -25% reduction in the total number of negative paths, without any major impact on total power of the designs.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP4-10

(Best Paper Award Candidate)
A SYNTHESIS-PARAMETER TUNING SYSTEM FOR AUTONOMOUS DESIGN-SPACE EXPLORATION
Speaker:
Matthew Ziegler, IBM T. J. Watson Research Center, US
Authors:
Matthew Ziegler¹, Hung-Yi Liu², George Gristede¹, Bruce Owens³, Ricardo Nigaglioni³ and Luca Carloni²
¹IBM T. J. Watson Research Center, US; ²Columbia University, US; ³IBM Systems and Technology Group, US
Abstract
Advanced logic and physical synthesis tools provide a vast num-ber of tunable parameters that can significantly impact physical design quality, but the complexity of the parameter design space requires intelligent search algorithms. To fully utilize the opti-mization potential of these tools, we propose SynTunSys, a sys-tem that adds a new level of abstraction between designers and design tools for managing the design space exploration process. SynTunSys takes control of the synthesis-parameter tuning pro-cess, i.e., job submission, results analysis, and next-step decision making, by automating a key portion of a human designer's decision process. We present the overall organization of Syn-TunSys, describe its main components, and provide results from employing it for the design of an industrial chip, the IBM z13 22nm high-performance server chip. During this major design, SynTunSys provided significant savings in human design effort and achieved a quality of results beyond what human designers alone could achieve, yielding on average a 36% improvement in total negative slack and a 7% power reduction.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP4-11

UNBOUNDED SAFETY VERIFICATION FOR HARDWARE USING SOFTWARE ANALYZERS
Speaker:
Rajdeep Mukherjee, University of Oxford, GB
Authors:
Rajdeep Mukherjee, Peter Schrammel, Daniel Kroening and Tom Melham, University of Oxford, GB
Abstract
Demand for scalable hardware verification is ever increasing. We propose an unbounded safety verification framework for hardware, at the heart of which is a software verifier. To this end, we synthesize Verilog at register transfer level into a software-netlist, represented as a word-level ANSI-C program. The proposed tool flow allows us to leverage the precision and scalability of state-of-the-art software verification techniques. In particular, we evaluate unbounded proof techniques, such as predicate abstraction, k-induction, interpolation, and IC3/PDR; and we compare the performance of verification tools from the hardware and software domains that use these techniques. To the best of our knowledge, this is the first attempt to perform unbounded verification of hardware using software analyzers.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP4-12

VERILOG2SMV: A TOOL FOR WORD-LEVEL VERIFICATION
Speaker:
Ahmed Irfan, Fondazione Bruno Kessler and University of Trento, IT
Authors:
Ahmed Irfan¹, Alessandro Cimatti², Alberto Griggio², Marco Roveri² and Roberto Sebastiani³
¹Fondazione Bruno Kessler and University of Trento, IT; ²Fondazione Bruno Kessler, IT; ³University of Trento, IT
Abstract
Verification is an essential step of the hardware design lifecycle. Usually verification is done at the gate level (Boolean level). We present verilog2smv, a tool that generates word-level model checking problems from Verilog designs augmented with assertions. A key aspect of our tool is that memories in the designs are treated without any form of abstraction. verilog2smv can be used for RTL verification by chaining with a word-level model checker like nuXmv. To this extent, we present also some experimental results over Verilog verification benchmarks, using verilog2smv + nuXmv as a tool-chain.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP4-13

TOWARDS FORMAL VERIFICATION OF REAL-WORLD SYSTEMC TLM PERIPHERAL MODELS - A CASE STUDY
Speaker:
Vladimir Herdt, University of Bremen, DE
Authors:
Hoang M. Le¹, Vladimir Herdt¹, Daniel Grosse¹ and Rolf Drechsler²
¹University of Bremen, DE; ²University of Bremen and DFKI, DE
Abstract
SystemC-based Virtual Prototypes (VPs) serve as reference models for various activities in the modern design flow and therefore, the functional correctness of each individual components and the VPs as a whole should be subjected to rigorous formal verification. In the last few years, notable progress on SystemC formal verification has been made. This paper presents a case study on applying a recent approach to formally verify TLM peripheral models. To the best of our knowledge, this is the first formal verification case study targeting this important class of VP components. First, we show how to bridge the gap between the industry-accepted modeling pattern for TLM peripheral models and the semantics currently supported by SystemC formal verification approaches. Then, we report verification results for the interrupt controller of the LEON3-based SoCRocket VP used by the European Space Agency and reflect on our experiences and lessons learned in the process.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP4-14

FREQUENCY SCHEDULING FOR RESILIENT CHIP MULTI-PROCESSORS OPERATING AT NEAR THRESHOLD VOLTAGE
Speaker:
Huawei Li, Chinese Academy of Sciences, CN
Authors:
Ying Wang, Huawei Li and Xiaowei Li, Chinese Academy of Sciences, CN
Abstract
With the recently proposed redundancy-based core salvaging technology, resilient processors can survive the threat of severe timing violation induced by near-threshold Vdd and function correctly at aggressive clock rates. In our observation, proactively disabling the weakest components that limit the core frequency can still maintain a higher throughput at Near Threshold Voltage (NTV) supply if the cores with defected components are salvaged at a low cost. In this work, a resilience-aware frequency scaling and mapping strategy that considers defected processor states in scheduling is proposed to exploit the fault-tolerant architectures for higher energy efficiency. In our evaluation, it is witnessed that typical resilient multi-core processors can achieve significantly higher performance per watt in experiments compared to conventional scheduling policy.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP4-15

(Best Paper Award Candidate)
A LOW OVERHEAD ERROR CONFINEMENT METHOD BASED ON APPLICATION STATISTICAL CHARACTERISTICS
Speaker:
Anupam Chattopadhyay, Nanyang Technological University, SG
Authors:
Zheng Wang¹, Georgios Karakonstantis² and Anupam Chattopadhyay³
¹RWTH-Aachen University, DE; ²Queen's University, GB; ³Nanyang Technological University, SG
Abstract
Reliability has emerged as a critical design constraint especially in memories. Designers have spent great efforts to guarantee fault free operation of the underlying silicon by adopting redundancy-based techniques, which essentially try to detect and correct every single error. However, such techniques come at a cost of large area, power and performance overheads which make many to doubt their efficiency especially for error resilient systems where 100% accuracy is not always required. In this paper, we present an alternative method focusing on the confinement of the resulting output error induced by any reliability issues. By focusing on memory faults, rather than correcting every single error the proposed method exploits the statistical characteristics of any target application and replaces any erroneous data with the best available estimate of that data. To realize the proposed method a RISC processor is augmented with custom instructions and special-purpose functional units. We apply the method on the proposed enhanced processor by studying the statistical characteristics of the various algorithms involved in a popular multimedia application. Our experimental results show that in contrast to state-of-the-art fault tolerance approaches, we are able to reduce runtime and area overhead by 71.3% and 83.3% respectively.
Download Paper (PDF; Only available from the DATE venue WiFi)

Visit us at DATE 2016