IP3 Interactive Presentations

Label	Presentation Title Authors
IP3-1	A FLEXIBLE INEXACT TMR TECHNIQUE FOR SRAM-BASED FPGAS Speaker: Akash Kumar, Technische Universität Dresden, DE Authors: Shyamsundar Venkataraman¹, Rui Santos¹ and Akash Kumar² ¹National University of Singapore, SG; ²Technische Universität Dresden, DE Abstract Single Event Upsets (SEUs) inadvertently change the logic memory and thereby the configuration of the Field Programmable Gate Arrays (FPGAs), leading to their incorrect functioning. Traditional methods to tolerate such faults include Triple Modular Redundancy (TMR). However, such method has a high overhead in terms of power and area. Moreover, the inexact methods used in ASICs to overcome this problem are not efficient when applied in FPGAs. Therefore, this paper proposes a novel technique based on heuristic to tolerate faults in SRAM-based FPGAs by using inexact modules in conjunction with TMR, thus reducing the area and power overhead of the design. Experiments run on various MCNC benchmark circuits show the accuracy of the proposed technique. They also show that the design solutions found through this technique only differ 0.52% on average from the optimal ones and savings up to 84.4% in terms of computation time can be reached on average. Download Paper (PDF; Only available from the DATE venue WiFi)
IP3-2	ACCURATE VERIFICATION OF RC POWER GRIDS Speaker: Mohammad Fawaz, University of Toronto, CA Authors: Mohammad Fawaz and Farid N. Najm, University of Toronto, CA Abstract The power distribution network (PDN) of an integrated circuit (IC) must undergo various checks throughout the design flow, in order to guarantee that the voltage fluctuations are within certain user-specified safety thresholds. Vectorless verification of the PDN is one approach for verification that requires little information about the on-die logic. This verification problem has been studied extensively over the past few years and has been generally solved by first discretizing time using a particular user-defined time-step. We investigate the effect of this time-step on the quality of the solutions produced (both exact and estimates). We also propose an efficient method to specify the time-step in a way to minimize the errors introduced by the voltage drop estimates. Download Paper (PDF; Only available from the DATE venue WiFi)
IP3-3	SECURITY ANALYSIS OF CYBER-PHYSICAL SYSTEMS ILLUSTRATED WITH AUTOMOTIVE CASE STUDY Speaker: Viacheslav Izosimov, KTH Royal Institute of Technology, SE Authors: Viacheslav Izosimov¹, Alexandros Asvestopoulos², Oscar Blomkvist² and Martin Törngren³ ¹Semcon, SE; ²Scania CV, SE; ³KTH Royal Institute of Technology, SE Abstract We present a method for systematic consideration of security attributes in development of cyber-physical systems. We evaluate our method in development of commercial vehicles that were so far unreasonably excluded from automotive security studies (despite the great importance of commercial vehicles for the society). We have conducted analysis of a known zero-cost non-physical attack, fine-tuned to our commercial vehicle (a truck), and considered countermeasures within the development flow. Download Paper (PDF; Only available from the DATE venue WiFi)
IP3-4	ONLINE HEURISTIC FOR THE MULTI-OBJECTIVE GENERALIZED TRAVELING SALESMAN PROBLEM Speaker: Joost van Pinxten, Eindhoven University of Technology, NL Authors: Joost van Pinxten¹, Marc Geilen¹, Twan Basten¹, Umar Waqas¹ and Lou Somers² ¹Eindhoven University of Technology, NL; ²Océ Technologies, NL Abstract Today's manufacturing systems are typically complex cyber-physical systems where the physical and control aspects interact with the scheduling decisions. Optimizing such facilities requires ordering jobs and configuring the manufacturing system for each job. This optimization problem can be described as a Multi-Objective Generalized TSP where conflicting objectives lead to a trade-off space. This is the first work to address this TSP variant, introducing a compositional heuristic suitable to online application. Download Paper (PDF; Only available from the DATE venue WiFi)
IP3-5	TOWARDS LOW OVERHEAD CONTROL FLOW CHECKING USING REGULAR STRUCTURED CONTROL Speaker: Zhiqi Zhu, The University of Texas at Dallas, US Authors: Zhiqi Zhu and Joseph Callenes-Sloan, The University of Texas at Dallas, US Abstract Abstract—With process scaling and the adoption of post- CMOS technologies, reliability has been brought to the forefront of modern computer system design. Among the different ways that hardware faults can manifest in a system, errors related to the control flow of a program tend to be the most difficult to handle when ensuring reliable computing. Errors in the sequencing of instructions executed are usually catastrophic, resulting in system hangs, crashes, and/or corrupted data. For this reason, conventional approaches rely on some form of general redundancy for detecting or recovering from a control flow error. Due to the power constraints of emerging systems however, these types of conservative approaches are quickly becoming infeasible. Control Flow Checking by Software Signatures (CFCSS) is a software-based technique for detecting control flow errors [1] that using assigned signatures rather than by using general redundancy. Unfortunately, the performance overhead for CFCSS can still be as high as 80%-90% for many applications. In this paper, we propose a novel method for reducing the overhead of control flow checking by exploiting the regular control structure found in many applications. Specifically, we observe that the alternating sequence of conditional and unconditional based control allows for the full control signatures to be computed at alternating basic blocks. Based on experimental results of the proposed approach, we observe that the overheads of the traditional methods are reduced on average by 25.9%. Download Paper (PDF; Only available from the DATE venue WiFi)
IP3-6	EMULATION-BASED HIERARCHICAL FAULT-INJECTION FRAMEWORK FOR COARSE-TO-FINE VULNERABILITY ANALYSIS OF HARDWARE-ACCELERATED APPROXIMATE ALGORITHMS Speaker: Theocharis Theocharides, University of Cyprus, CY Authors: Ioannis Chadjiminas, Ioannis Savva, Christos Kyrkou, Maria K. Michael and Theocharis Theocharides, University of Cyprus, CY Abstract This paper proposes a hierarchical fault injection emulation framework tailored to the structure of complex and large application-specific circuits, that performs vulnerability analysis of the system for single event upsets (SEUs) at different design granularities in real-time. In particular, the framework allows for efficient probabilistic modelling of the SEU impact, making it particularly applicable for hardware-accelerated approximate applications such as multimedia, computer vision and image/signal processing, due to its high processing speed and real-time capabilities. The framework is emulated on an FPGA-based platform and evaluated using a depth computation kernel, both in standalone manner as well as within a robotic obstacle avoidance application. Download Paper (PDF; Only available from the DATE venue WiFi)
IP3-7	TECHNOLOGY TRANSFER IN COMPUTING SYSTEMS: THE TETRACOM APPROACH Speaker and Author: Rainer Leupers, RWTH Aachen University, DE Abstract TETRACOM is an ongoing EU FP7 Coordination Action with the ambition to boost small to medium scale academia-to-industry technology transfer in all domains of computing systems. The project primarily operates via competitive open calls for individual Technology Transfer Projects (TTPs). Each TTP performs a well-defined bilateral transfer activity between one European academic partner and one industry partner. TETRACOM coordinates all TTPs and provides technology transfer advice and co-funding. This paper describes TETRACOM´s experimental concept and project structure. It summarizes preliminary lessons learned after more than two project years and successful management of 30+ individual TTPs. Download Paper (PDF; Only available from the DATE venue WiFi)
IP3-8	ENERGY VS. RELIABILITY TRADE-OFFS EXPLORATION IN BIOMEDICAL ULTRA-LOW POWER DEVICES Speaker: Loris Duch, École Polytechnique Fédérale de Lausanne (EPFL), CH Authors: Loris Duch, Pablo Garcia del Valle, David Atienza, Shrikanth Ganapathy and Andreas Burg, École Polytechnique Fédérale de Lausanne (EPFL), CH Abstract State-of-the-art wearable devices such as embedded biomedical monitoring systems apply voltage scaling to lower as much as possible their energy consumption and achieve longer battery lifetimes. While embedded memories often rely on Error Correction Codes (ECC) for error protection, in this paper we explore how the characteristics of biomedical applications can be exploited to develop new techniques with lower power overhead. We then introduce the Dynamic eRror compEnsation And Masking (DREAM) technique, that provides partial memory protection with less area and power overheads than ECC. Different tradeoffs between the error correction ability of the techniques and their energy consumption are examined to conclude that, when properly applied, DREAM consumes 21% less energy than a traditional ECC with Single Error Correction and Double Error Detection (SEC/DED) capabilities. Download Paper (PDF; Only available from the DATE venue WiFi)
IP3-9	A MACHINE LEARNING APPROACH FOR MEDICATION ADHERENCE MONITORING USING BODY-WORN SENSORS Speaker: Hassan Ghasemzadeh, Washington State University, US Authors: Niloofar Hezar Jaribi, Ramin Fallahzadeh and Hassan Ghasemzadeh, Washington State University, US Abstract One of the most important challenges in current healthcare systems is medication non-adherence, which has irrevocable outcomes. Although many technologies have been developed for medication adherence monitoring, the reliability and cost-effectiveness of these technologies are not well understood to date. This paper presents a medication adherence monitoring system by user-activity tracking based on wrist-band wearable sensors. We develop machine learning algorithms that track wrist motions in real-time and identify medication intake activities. We propose a novel data analysis pipeline to reliably detect medication adherence by examining single-wrist motions. Our system achieves an accuracy of 78.3% in adherence detection without need for medication pillboxes and with only one sensor worn on either of the wrists. The accuracy of our algorithm is only 7.9% lower than a system with two sensors that track motions of both wrists. Download Paper (PDF; Only available from the DATE venue WiFi)
IP3-10	REQUIREMENTS-CENTRIC CLOSED-LOOP VALIDATION OF IMPLANTABLE CARDIAC DEVICES Speaker: Partha Roop, The University of Auckland, NZ Authors: Weiwei Ai, Nitish Patel and Partha Roop, The University of Auckland, NZ Abstract Implantable medical devices are recommended by physicians to sustain life while improving the overall quality of life of the patients. In spite of the rigorous testing, there have been numerous failures and associated recalls which suggest that completeness of the testing is elusive. We propose a new validation framework based on formal methods for real-time closed-loop validation of medical devices. The proposed approach includes a synchronous observer acting both as an automated oracle and also as a requirements coverage monitor. The observer combines an on-line testing adequacy evaluation module together with a heuristic learning module. This methodology was applied to validate a pacemaker over a virtual heart model. A subset of the requirements was used to test its efficacy. The results show that the proposed methodology can, in real-time, evaluate the test adequacy and hence guide the on-line test case generation to maximize the requirements coverage. Download Paper (PDF; Only available from the DATE venue WiFi)
IP3-11	LOW NORMALIZED ENERGY DERIVATION ASYNCHRONOUS CIRCUIT SYNTHESIS FLOW THROUGH FORK-JOIN SLACK MATCHING FOR CRYPTOGRAPHIC APPLICATIONS Speaker: Nan Liu, Nanyang Technological University, SG Authors: Nan Liu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee and Joseph S. Chang, Nanyang Technological University, SG Abstract In this paper, an automatic synthesis flow of asynchronous (async) Quasi-Delay-Insensitive (QDI) circuits for cryptographic applications is presented. The synthesis flow accepts Verilog netlists as primary inputs, in part leverages on commercial electronic design automation tools for synthesis and verifications, and relies heavily on the proposed translation processes for async netlist conversion and optimization. Particularly, a three-step synchronous-to-asynchronous-direct-translation (SADT) process is proposed. The first step is to translate a Verilog netlist into a direct circuit graph, allowing us to model QDI pipelines for performance analysis based on the same netlist function. Second, graph coarsening in combination with dynamic programing is adopted to analyze the fork-join slack matching of the QDI pipelines, aiming to balance the pipeline depths in any fork-join pipelines to optimize the system performance, and to reduce energy variations of the overall pipelines to against power-analysis-attack. The last step is to insert async local controllers/gates to ensure the async circuits consistent with QDI protocol, hence enhancing its timing robustness to accommodate Process-Voltage-Temperature variations. We show that, on the basis of simulations on the ISCAS benchmark circuits, the QDI circuits based on our proposed automatic synthesis flow are on average 20% faster and feature 30% less normalized energy derivations than un-optimized circuits. Download Paper (PDF; Only available from the DATE venue WiFi)
IP3-12	A LIFETIME-AWARE RUNTIME MAPPING APPROACH FOR MANYCORE SYSTEMS IN THE DARK SILICON ERA Speaker: Mohammad-Hashem Haghbayan, University of Turku, FI Authors: Mohammad-Hashem Haghbayan¹, Antonio Miele², Amir-Mohammad Rahmani³, Pasi Liljeberg¹ and Hannu Tenhunen³ ¹University of Turku, FI; ²Politecnico di Milano, IT; ³KTH Royal Institute of Technology and University of Turku, FI Abstract In this paper, we propose a novel lifetime reliability-aware resource management approach for many-core architectures. The approach is based on hierarchical architecture, composed of a long-term runtime reliability analysis unit and a short-term runtime mapping unit. The former periodically analyses the aging status of the various processing units with respect to a target value specified by the designer, and performs recovery actions on highly stressed cores. The calculated reliability metrics are utilized in runtime mapping of the newly arrived applications to maximize the performance of the system while fulfilling reliability requirements and the available power budget. Our extensive experimental results reveal that the proposed reliability-aware approach can efficiently select the processing cores to be used over time in order to enhance the reliability at the end of the operational life (up to 62%) while offering the comparable performance level of the state-of-the-art runtime mapping approach. Download Paper (PDF; Only available from the DATE venue WiFi)

Label

Presentation Title
Authors

IP3-1

A FLEXIBLE INEXACT TMR TECHNIQUE FOR SRAM-BASED FPGAS
Speaker:
Akash Kumar, Technische Universität Dresden, DE
Authors:
Shyamsundar Venkataraman¹, Rui Santos¹ and Akash Kumar²
¹National University of Singapore, SG; ²Technische Universität Dresden, DE
Abstract
Single Event Upsets (SEUs) inadvertently change the logic memory and thereby the configuration of the Field Programmable Gate Arrays (FPGAs), leading to their incorrect functioning. Traditional methods to tolerate such faults include Triple Modular Redundancy (TMR). However, such method has a high overhead in terms of power and area. Moreover, the inexact methods used in ASICs to overcome this problem are not efficient when applied in FPGAs. Therefore, this paper proposes a novel technique based on heuristic to tolerate faults in SRAM-based FPGAs by using inexact modules in conjunction with TMR, thus reducing the area and power overhead of the design. Experiments run on various MCNC benchmark circuits show the accuracy of the proposed technique. They also show that the design solutions found through this technique only differ 0.52% on average from the optimal ones and savings up to 84.4% in terms of computation time can be reached on average.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP3-2

ACCURATE VERIFICATION OF RC POWER GRIDS
Speaker:
Mohammad Fawaz, University of Toronto, CA
Authors:
Mohammad Fawaz and Farid N. Najm, University of Toronto, CA
Abstract
The power distribution network (PDN) of an integrated circuit (IC) must undergo various checks throughout the design flow, in order to guarantee that the voltage fluctuations are within certain user-specified safety thresholds. Vectorless verification of the PDN is one approach for verification that requires little information about the on-die logic. This verification problem has been studied extensively over the past few years and has been generally solved by first discretizing time using a particular user-defined time-step. We investigate the effect of this time-step on the quality of the solutions produced (both exact and estimates). We also propose an efficient method to specify the time-step in a way to minimize the errors introduced by the voltage drop estimates.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP3-3

SECURITY ANALYSIS OF CYBER-PHYSICAL SYSTEMS ILLUSTRATED WITH AUTOMOTIVE CASE STUDY
Speaker:
Viacheslav Izosimov, KTH Royal Institute of Technology, SE
Authors:
Viacheslav Izosimov¹, Alexandros Asvestopoulos², Oscar Blomkvist² and Martin Törngren³
¹Semcon, SE; ²Scania CV, SE; ³KTH Royal Institute of Technology, SE
Abstract
We present a method for systematic consideration of security attributes in development of cyber-physical systems. We evaluate our method in development of commercial vehicles that were so far unreasonably excluded from automotive security studies (despite the great importance of commercial vehicles for the society). We have conducted analysis of a known zero-cost non-physical attack, fine-tuned to our commercial vehicle (a truck), and considered countermeasures within the development flow.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP3-4

ONLINE HEURISTIC FOR THE MULTI-OBJECTIVE GENERALIZED TRAVELING SALESMAN PROBLEM
Speaker:
Joost van Pinxten, Eindhoven University of Technology, NL
Authors:
Joost van Pinxten¹, Marc Geilen¹, Twan Basten¹, Umar Waqas¹ and Lou Somers²
¹Eindhoven University of Technology, NL; ²Océ Technologies, NL
Abstract
Today's manufacturing systems are typically complex cyber-physical systems where the physical and control aspects interact with the scheduling decisions. Optimizing such facilities requires ordering jobs and configuring the manufacturing system for each job. This optimization problem can be described as a Multi-Objective Generalized TSP where conflicting objectives lead to a trade-off space. This is the first work to address this TSP variant, introducing a compositional heuristic suitable to online application.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP3-5

TOWARDS LOW OVERHEAD CONTROL FLOW CHECKING USING REGULAR STRUCTURED CONTROL
Speaker:
Zhiqi Zhu, The University of Texas at Dallas, US
Authors:
Zhiqi Zhu and Joseph Callenes-Sloan, The University of Texas at Dallas, US
Abstract
Abstract—With process scaling and the adoption of post- CMOS technologies, reliability has been brought to the forefront of modern computer system design. Among the different ways that hardware faults can manifest in a system, errors related to the control flow of a program tend to be the most difficult to handle when ensuring reliable computing. Errors in the sequencing of instructions executed are usually catastrophic, resulting in system hangs, crashes, and/or corrupted data. For this reason, conventional approaches rely on some form of general redundancy for detecting or recovering from a control flow error. Due to the power constraints of emerging systems however, these types of conservative approaches are quickly becoming infeasible. Control Flow Checking by Software Signatures (CFCSS) is a software-based technique for detecting control flow errors [1] that using assigned signatures rather than by using general redundancy. Unfortunately, the performance overhead for CFCSS can still be as high as 80%-90% for many applications. In this paper, we propose a novel method for reducing the overhead of control flow checking by exploiting the regular control structure found in many applications. Specifically, we observe that the alternating sequence of conditional and unconditional based control allows for the full control signatures to be computed at alternating basic blocks. Based on experimental results of the proposed approach, we observe that the overheads of the traditional methods are reduced on average by 25.9%.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP3-6

EMULATION-BASED HIERARCHICAL FAULT-INJECTION FRAMEWORK FOR COARSE-TO-FINE VULNERABILITY ANALYSIS OF HARDWARE-ACCELERATED APPROXIMATE ALGORITHMS
Speaker:
Theocharis Theocharides, University of Cyprus, CY
Authors:
Ioannis Chadjiminas, Ioannis Savva, Christos Kyrkou, Maria K. Michael and Theocharis Theocharides, University of Cyprus, CY
Abstract
This paper proposes a hierarchical fault injection emulation framework tailored to the structure of complex and large application-specific circuits, that performs vulnerability analysis of the system for single event upsets (SEUs) at different design granularities in real-time. In particular, the framework allows for efficient probabilistic modelling of the SEU impact, making it particularly applicable for hardware-accelerated approximate applications such as multimedia, computer vision and image/signal processing, due to its high processing speed and real-time capabilities. The framework is emulated on an FPGA-based platform and evaluated using a depth computation kernel, both in standalone manner as well as within a robotic obstacle avoidance application.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP3-7

TECHNOLOGY TRANSFER IN COMPUTING SYSTEMS: THE TETRACOM APPROACH
Speaker and Author:
Rainer Leupers, RWTH Aachen University, DE
Abstract
TETRACOM is an ongoing EU FP7 Coordination Action with the ambition to boost small to medium scale academia-to-industry technology transfer in all domains of computing systems. The project primarily operates via competitive open calls for individual Technology Transfer Projects (TTPs). Each TTP performs a well-defined bilateral transfer activity between one European academic partner and one industry partner. TETRACOM coordinates all TTPs and provides technology transfer advice and co-funding. This paper describes TETRACOM´s experimental concept and project structure. It summarizes preliminary lessons learned after more than two project years and successful management of 30+ individual TTPs.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP3-8

ENERGY VS. RELIABILITY TRADE-OFFS EXPLORATION IN BIOMEDICAL ULTRA-LOW POWER DEVICES
Speaker:
Loris Duch, École Polytechnique Fédérale de Lausanne (EPFL), CH
Authors:
Loris Duch, Pablo Garcia del Valle, David Atienza, Shrikanth Ganapathy and Andreas Burg, École Polytechnique Fédérale de Lausanne (EPFL), CH
Abstract
State-of-the-art wearable devices such as embedded biomedical monitoring systems apply voltage scaling to lower as much as possible their energy consumption and achieve longer battery lifetimes. While embedded memories often rely on Error Correction Codes (ECC) for error protection, in this paper we explore how the characteristics of biomedical applications can be exploited to develop new techniques with lower power overhead. We then introduce the Dynamic eRror compEnsation And Masking (DREAM) technique, that provides partial memory protection with less area and power overheads than ECC. Different tradeoffs between the error correction ability of the techniques and their energy consumption are examined to conclude that, when properly applied, DREAM consumes 21% less energy than a traditional ECC with Single Error Correction and Double Error Detection (SEC/DED) capabilities.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP3-9

A MACHINE LEARNING APPROACH FOR MEDICATION ADHERENCE MONITORING USING BODY-WORN SENSORS
Speaker:
Hassan Ghasemzadeh, Washington State University, US
Authors:
Niloofar Hezar Jaribi, Ramin Fallahzadeh and Hassan Ghasemzadeh, Washington State University, US
Abstract
One of the most important challenges in current healthcare systems is medication non-adherence, which has irrevocable outcomes. Although many technologies have been developed for medication adherence monitoring, the reliability and cost-effectiveness of these technologies are not well understood to date. This paper presents a medication adherence monitoring system by user-activity tracking based on wrist-band wearable sensors. We develop machine learning algorithms that track wrist motions in real-time and identify medication intake activities. We propose a novel data analysis pipeline to reliably detect medication adherence by examining single-wrist motions. Our system achieves an accuracy of 78.3% in adherence detection without need for medication pillboxes and with only one sensor worn on either of the wrists. The accuracy of our algorithm is only 7.9% lower than a system with two sensors that track motions of both wrists.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP3-10

REQUIREMENTS-CENTRIC CLOSED-LOOP VALIDATION OF IMPLANTABLE CARDIAC DEVICES
Speaker:
Partha Roop, The University of Auckland, NZ
Authors:
Weiwei Ai, Nitish Patel and Partha Roop, The University of Auckland, NZ
Abstract
Implantable medical devices are recommended by physicians to sustain life while improving the overall quality of life of the patients. In spite of the rigorous testing, there have been numerous failures and associated recalls which suggest that completeness of the testing is elusive. We propose a new validation framework based on formal methods for real-time closed-loop validation of medical devices. The proposed approach includes a synchronous observer acting both as an automated oracle and also as a requirements coverage monitor. The observer combines an on-line testing adequacy evaluation module together with a heuristic learning module. This methodology was applied to validate a pacemaker over a virtual heart model. A subset of the requirements was used to test its efficacy. The results show that the proposed methodology can, in real-time, evaluate the test adequacy and hence guide the on-line test case generation to maximize the requirements coverage.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP3-11

LOW NORMALIZED ENERGY DERIVATION ASYNCHRONOUS CIRCUIT SYNTHESIS FLOW THROUGH FORK-JOIN SLACK MATCHING FOR CRYPTOGRAPHIC APPLICATIONS
Speaker:
Nan Liu, Nanyang Technological University, SG
Authors:
Nan Liu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee and Joseph S. Chang, Nanyang Technological University, SG
Abstract
In this paper, an automatic synthesis flow of asynchronous (async) Quasi-Delay-Insensitive (QDI) circuits for cryptographic applications is presented. The synthesis flow accepts Verilog netlists as primary inputs, in part leverages on commercial electronic design automation tools for synthesis and verifications, and relies heavily on the proposed translation processes for async netlist conversion and optimization. Particularly, a three-step synchronous-to-asynchronous-direct-translation (SADT) process is proposed. The first step is to translate a Verilog netlist into a direct circuit graph, allowing us to model QDI pipelines for performance analysis based on the same netlist function. Second, graph coarsening in combination with dynamic programing is adopted to analyze the fork-join slack matching of the QDI pipelines, aiming to balance the pipeline depths in any fork-join pipelines to optimize the system performance, and to reduce energy variations of the overall pipelines to against power-analysis-attack. The last step is to insert async local controllers/gates to ensure the async circuits consistent with QDI protocol, hence enhancing its timing robustness to accommodate Process-Voltage-Temperature variations. We show that, on the basis of simulations on the ISCAS benchmark circuits, the QDI circuits based on our proposed automatic synthesis flow are on average 20% faster and feature 30% less normalized energy derivations than un-optimized circuits.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP3-12

A LIFETIME-AWARE RUNTIME MAPPING APPROACH FOR MANYCORE SYSTEMS IN THE DARK SILICON ERA
Speaker:
Mohammad-Hashem Haghbayan, University of Turku, FI
Authors:
Mohammad-Hashem Haghbayan¹, Antonio Miele², Amir-Mohammad Rahmani³, Pasi Liljeberg¹ and Hannu Tenhunen³
¹University of Turku, FI; ²Politecnico di Milano, IT; ³KTH Royal Institute of Technology and University of Turku, FI
Abstract
In this paper, we propose a novel lifetime reliability-aware resource management approach for many-core architectures. The approach is based on hierarchical architecture, composed of a long-term runtime reliability analysis unit and a short-term runtime mapping unit. The former periodically analyses the aging status of the various processing units with respect to a target value specified by the designer, and performs recovery actions on highly stressed cores. The calculated reliability metrics are utilized in runtime mapping of the newly arrived applications to maximize the performance of the system while fulfilling reliability requirements and the available power budget. Our extensive experimental results reveal that the proposed reliability-aware approach can efficiently select the processing cores to be used over time in order to enhance the reliability at the end of the operational life (up to 62%) while offering the comparable performance level of the state-of-the-art runtime mapping approach.
Download Paper (PDF; Only available from the DATE venue WiFi)

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