Date: Thursday 17 March 2016
Time: 16:00 - 17:30
Location / Room: Konferenz 1

Chair:
Oliver Bringmann, University of Tuebingen, DE

Co-Chair:
Dirk Stroobandt, Ghent University, BE

This session discusses a wide range of innovative techniques from instruction scheduling to mobile virtualization to characterize and improve system resilience and robustness.

Time	Label	Presentation Title Authors
16:00	12.3.1	EFFECT OF LFSR SEEDING, SCRAMBLING AND FEEDBACK POLYNOMIAL ON STOCHASTIC COMPUTING ACCURACY Speaker: Jason H. Anderson, University of Toronto, CA Authors: Jason H. Anderson1, Yuko Hara-Azumi2 and Shigeru Yamashita3 1University of Toronto, CA; 2Tokyo Institute of Technology, JP; 3Ritsumeikan University, JP Abstract Stochastic computing (SC) has received attention recently as a paradigm to improve energy efficiency and fault tolerance. SC uses hardware-generated random bitstreams to represent numbers in the [0:1] range - the number represented is the probability of a bit in the stream being logic-1. The generation of random bitstreams is typically done using linear-feedback shift register (LFSR)-based random number generators. In this paper, we consider how best to design such LFSR-based stochastic bitstream generators, as a means of improving the accuracy of stochastic computing. Three design criteria are evaluated: 1) LFSR seed selection, 2) the utility of scrambling LFSR output bits, and 3) the LFSR polynomials (i.e. locations of the feedback taps) and whether they should be unique vs. uniform across stream generators. For a recently proposed multiplexer-based stochastic logic architecture, we demonstrate that careful seed selection can improve accuracy results vs. the use of arbitrarily selected seeds. For example, we show that stochastic logic with seed-optimized 255-bit stream lengths achieves accuracy better than that of using 1023-bit stream lengths with arbitrary seeds: an improvement of over 4X in energy for equivalent accuracy Download Paper (PDF; Only available from the DATE venue WiFi)
16:30	12.3.2	EFFICIENT PROGRAM TRACING AND MONITORING THROUGH POWER CONSUMPTION - WITH A LITTLE HELP FROM THE COMPILER Speaker: Carlos Moreno, University of Waterloo, CA Authors: Carlos Moreno, Sean Kauffman and Sebastian Fischmeister, University of Waterloo, CA Abstract Ensuring correctness and enforcing security are growing concerns given the complexity of modern connected devices and safety-critical systems. A promising approach is non-intrusive runtime monitoring through reconstruction of program execution traces from power consumption measurements. This can be used for verification, validation, debugging, and security purposes. In this paper, we propose a framework for increasing the effectiveness of power-based program tracing techniques. These systems determine the most likely block of source code that produced an observed power trace (CPU power consumption as a function of time). Our framework maximizes distinguishability between power traces for different code blocks. To this end, we provide a special compiler optimization stage that reorders intermediate representation (IR) and determines the reorderings that lead to power traces with highest distances between each other, thus reducing the probability of misclassification. Our work includes an experimental evaluation, using LLVM for an ARM architecture. Experimental results confirm the effectiveness of our technique. Download Paper (PDF; Only available from the DATE venue WiFi)
17:00	12.3.3	FLIC: FAST, LIGHTWEIGHT CHECKPOINTING FOR MOBILE VIRTUALIZATION USING NVRAM Speaker: Kan Zhong, Chongqing University, CN Authors: Kan Zhong1, Duo Liu1, Liang Liang1, Linbo Long1, Yi Lin1 and Zili Shao2 1Chongqing University, CN; 2The Hong Kong Polytechnic University, HK Abstract Checkpointing is a key enabler of hibernation, live migration and fault-tolerance for virtual machines (VMs) in mobile devices. However, checkpointing a VM is usually heavyweight: the VM's entire memory needs to be dumped to storage, which induces a significant amount of (slow) I/O operations, degrading system performance and user experience. In this paper, we propose FLIC, a fast and lightweight checkpointing machinery for virtualized mobile devices by taking advantages of recent byte-addressable, non-volatile memory (NVRAM). Instead of saving the VM's entire memory to storage, we store its working set pages in NVRAM, avoiding accessing slow flash memory (compared to server-grade SSDs). To cope with the energy constraint of mobile systems, we further deduplicate VM snapshots, reducing the VM's image size and saving storage space. Experimental results based on an Exynos 5250 SoC show that our approach can effectively improve the performance of checkpointing in mobile virutalization and save energy. Download Paper (PDF; Only available from the DATE venue WiFi)
17:15	12.3.4	PAIS: PARALLELIZATION AWARE INSTRUCTION SCHEDULING FOR IMPROVING SOFT-ERROR RELIABILITY OF GPU-BASED SYSTEMS Speaker: Mohammad Abdullah Al Faruque, University of California, Irvine, US Authors: Haeseung Lee, Hsinchung Chen and Mohammad Abdullah Al Faruque, University of California, Irvine, US Abstract For decades the semiconductor industry has been driven by Moore's Law and performed aggressive technology scaling to achieve low-power and high-performance. Meanwhile, the semiconductor industry has faced severe reliability challenges like soft-error. Many methodologies (such as redundancy methodologies) have been proposed to improve the soft-error reliability of GPU based systems. However, the GPU compiler has yet to be considered for improving the soft-error reliability of the GPU. In this paper, we propose a novel GPU architecture-aware compilation methodology to further improve the soft-error reliability. The proposed methodology jointly considers the parallel behavior of the GPU and the applications and minimizes the vulnerability of the GPU applications during instruction scheduling. The experimental results show that our methodology is able to perform the scheduling within 5.88 seconds on average and achieves soft-error reliability improvement up to 40% compared to the state-of-the-art compilation techniques. The results show that the performance and power overheads of our methodology are less than 10% in most of the cases. Download Paper (PDF; Only available from the DATE venue WiFi)
17:30		End of session