W04 DUHDe – 2nd Workshop on Design Automation for Understanding Hardware Designs
Agenda
| Time | Label | Session |
|---|---|---|
| 08:30 | W04.1 | Opening session |
| 08:30 | W04.1.1 | Opening session Goerschwin Fey1 and Emmanuelle Encrenaz-Tiphene2 1Univ. of Bremen, DE; 2UPMC/LIP6, FR |
| 08:40 | W04.2 | Invited talk 1 |
| 08:40 | W04.2.1 | Practical applications of hardware design understanding using formal methods Eli Arbel, IBM Research, Haifa, IL |
| 09:20 | W04.3 | Technical session 1 |
| 09:20 | W04.3.1 | SystemC-Based Loose Models: RTL Abstraction for Design Understanding Saif Abrar Syed, Maksim Jenihhin and Jaan Raik, Tallinn University of Technology, EE |
| 09:45 | W04.3.2 | Ecore Model Generation from SystemC/C++ Implementations Jannis Stoppe1 and Rolf Drechsler2 1Universität Bremen, DE; 2University of Bremen/DFKI GmbH, DE |
| 10:10 | W04.3.3 | Towards analysing feature locations through testing traces with BUT4Reuse Jabier Martinez1, Jan Malburg2, Tewfik Ziadi3 and Goerschwin Fey4 1SnT, University of Luxembourg, LU; 2University of Bremen, DE; 3LiP6, University Pierre and Marie Curie, FR; 4Univ. of Bremen, DE |
| 10:35 | W04.4 | Coffee break |
| 11:00 | W04.5 | Invited talk 2 |
| 11:00 | W04.5.1 | Assertion Mining Shobha Vasudevan, University of Illinois at Urbana-Champaign, US |
| 11:50 | W04.6 | Poster teasers |
| 11:50 | W04.6.1 | Poster teasers |
| 12:00 | W04.7 | Lunch |
| 13:00 | W04.8 | Technical session 2 |
| 13:00 | W04.8.1 | Learning Grammars for Assertion Creation from Natural Language Christopher Harris1 and Ian Harris2 1University of California Irvine, US; 2University of Californa Irvine, US |
| 13:25 | W04.8.2 | A Binding Method for Hierarchical Testability Using Results of Test Environment Generation Jun Nishimaki1, Toshinori Hosokawa2 and Hideo Fujiwara3 1Graduate School of Industrial Technology, Nihon University, JP; 2Nihon University, JP; 3Faculty of Informatics, Osaka Gakuin University, JP |
| 13:50 | W04.9 | Invited talk 3 |
| 13:50 | W04.9.1 | Parallelization of SystemC-TLM simulations, and modelling of time and power consumption Matthieu Moy, Verimag, Grenoble, FR |
| 14:40 | W04.10 | Poster session and coffee break |
| 14:40 | W04.10.1 | Is there a chance that computers understand analog design? Ramy Iskander1, Farakh Javid2 and marie-Minerve Louerat3 1Université Pierre et Marie Curie, FR; 2LIP6 Laboratory, FR; 3UNiversity Pierre & Marie Curie, LIP6, FR |
| 14:40 | W04.10.2 | Understanding the Heterogeneous Hardware: Do not forget the interconnection! Liliana Andrade1, Cédric Ben Aoun1, Benoît Vernay2, Torsten Maehne3, Francois Pecheux4 and marie-Minerve Louerat5 1UPMC - LIP6, FR; 2SU-UPMC/CNRS, LIP6, FR; 3Sorbonne Universités, UPMC Univ Paris 06, FR; 4UPMC/LIP6, FR; 5UNiversity Pierre & Marie Curie, LIP6, FR |
| 14:40 | W04.10.3 | AMS System-level exploration and verification using UVM in SystemC and SystemC AMS Yao Li1, Zhi Wang1, Francois Pecheux2, marie-Minerve Louerat3, Martin Barnasconi4, Thilo Voertler5 and Karsten Einwich5 1UPMC-LIP6, FR; 2UPMC/LIP6, FR; 3UNiversity Pierre & Marie Curie, LIP6, FR; 4NXP Semiconductors, NL; 5Fraunhofer IIS/EAS, DE |
| 14:40 | W04.10.4 | Debugging Hardware Designs Using Dynamic Dependency Graphs Jan Malburg1, Alexander Finder2 and Goerschwin Fey3 1University of Bremen, DE; 2Aventon GmbH, DE; 3Univ. of Bremen, DE |
| 15:30 | W04.11 | Technical session 3 |
| 15:30 | W04.11.1 | A simulator to understand the effects of fault injection attacks on a microcontroller Nicolas Moro1, Karine Heydemann2, Bruno Robisson3 and Emmanuelle Encrenaz-Tiphene4 1CEA, FR; 2LIP6 / University Pierre et Marie Curie, FR; 3CEA-Leti, FR; 4UPMC/LIP6, FR |
| 15:55 | W04.12 | Panel |
| Panelists: Panelists: Lyes Benalycherif1, Dominique Borrione2, Franco Fummi3 and Jaan Raik4 1STMicroelectronics, FR; 2TIMA, FR; 3Universita' di Verona, IT; 4Tallinn University of Technology, Department of Computer Engineering, EE |
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