Chair:
Mehdi Tahoori, Karlsruhe Institute of Technology, DE

The interaction between spin and orbital magnetism is responsible for some of the most important magnetic phenomena, such as the magnetocrystalline anisotropy and the anisotropic magnetoresistance. By locking the spin to the direction of motion, the spin-orbit interaction can additionally give rise to strong torques on the magnetization when an electric current is injected in the plane of a ferromagnet/heavy metal bilayer. Such torques are strong enough to induce magnetization reversal, and can be reversed by inverting the polarity of the current. These features, together with the in-plane current injection geometry, allow for fabricating three-terminal magnetic tunnel junction devices for novel memory and logic applications. Furthermore, spin-orbit torque magnetization switching is an ultrafast process with minimum incubation time, thus leading to a short read/write access time. 

In this talk we will present an overview of:

• Spin-orbit torque phenomena
• Material issues
• Device applications
• Ultrafast switching

Chair:
Mehdi Tahoori, Karlsruhe Institute of Technology, DE

Most of recent research on MRAM-based non-volatile logic and memories is considering Spin Transfer Torque Magnetic Tunnel Junctions with perpendicular-to-plane anisotropy (STTpe-MTJ). However, this technology suffers from limitations mainly due to the fact that it uses the same writing and reading paths. It is subject to high read disturb failure rates, meaning that a Magnetic Tunnel Junction (MTJ) can be written during a reading phase, in particular in case of high speed writing. Moreover, it has a limited endurance since the writing current flows through the tunnel barrier and damages it, especially when the polarization of the MTJ is approaching its breakdown voltage when writing. A much more recent technology enables to avoid such problems. Indeed Spin Orbit Torque Magnetic Tunnel Junctions (SOT-MTJ) have 3 terminals, enabling to separate the writing path from the reading path. These leads to a quasi-infinite endurance since the writing current flows underneath the SOT-MTJ in a conducting layer, and to a high reliability since there is no read disturb risk thanks to the use of 2 separate paths.

This talk will address the following topics:

• SOT-MTJ compact model for accurate electrical ASIC simulations
• Hybrid Magnetic / CMOS process design-kit and flow for full custom and digital ASICs
• Novel architectures of SOT-MTJ based standard cells and integration in the digital design flow
• Novel architecture of SOT-MTJ based MRAM

Chair:
Guillaume Prenat, Spintec / CEA-CNRS, FR

This talk overviews the architecture and system-level aspects in the design of SOT-MRAM as a part of the cache hierarchy. We will discuss how various features of the SOT-MRAM can be modeled by the memory system simulators and the design space for a hybrid memory architecture consisting of various flavors of MRAM and SRAM can be explored. Particularly this session presents performance, power, area, and reliability tradeoffs in the design of SOT-MRAM at various levels of cache hirerachy and compares them with STT-MRAM counterpart as well as traditional SRAM memories.