Date: Thursday 21 March 2013
Time: 12:00 - 14:00
Location / Room: Booth 46, Exhibition
Time | Label | Presentation Title Authors |
---|---|---|
12:00 | UB10.1 | THE MATISSE MATLAB COMPILER Authors: João Cardoso1, João Bispo1, Pedro Pinto1, Ricardo Nobre1, Tiago Carvalho1 and Pedro Diniz2 1University of Porto, PT; 2INESC-ID, PT Abstract |
12:00 | UB10.2 | SYNTHORUS-2: AUTOMATIC PROTOTYPING ON FPGA FROM PSL Authors: Fatemeh Javaheri, Katell Morin‐Allory, Alexandre Porcher and Dominique Borrione, TIMA Lab, FR Abstract |
12:00 | UB10.3 | FPGA-BASED IN SYSTEM MULTIPLE LRU CACHE SIMULATION Authors: Josef Schneider, Jorgen Peddersen and Sridevan Parameswaran, University of New South Wales, AU Abstract |
12:00 | UB10.4 | FLEXIBLE AND HIGH-SPEED SYSTEM-LEVEL PERFORMANCE ANALYSIS USING HARDWARE-ACCELERATED SIMULATION Authors: Sascha Bischoff1, Andreas Sandberg2, Andreas Hansson3, Dam Sunwoo4, Ali G. Saidi4, Matthew Horsnell3 and Bashir M. Al-Hashimi1 1University of Southampton, UK; 2Uppsala University, SE; 3ARM, UK; 4ARM, US Abstract |
12:00 | UB10.5 | EDA FOR SYSTEM LEVEL VERIFICATION: AN ADAPTIVE SYSTEM LEVEL VERIFICATION ENVIRONMENT Authors: Hassan Sohofi and Zainalabedin Navabi, University of Tehran, IR Abstract |
12:00 | UB10.6 | DAEDALUS^RT: A DESIGN FLOW FOR HARD-REAL-TIME EMBEDDED STREAMING SYSTEMS Authors: Mohamed Bamakhrama, Jiali Teddy Zhai, Sven van Haastregt and Todor Stefanov, Leiden University, NL Abstract |
12:00 | UB10.7 | SYNTHESIZING ABSTRACT COMMUNICATIONS TO RTL STANDARD BUS STRUCTURES Authors: Somayeh Sadeghi-Kohan, Rasoul Jafari, Ghazaleh Vazhbakht, Parastoo Kamranfar, Reza Namazian, Mahya Saffarpour and Zain Navabi, University of Tehran, IR Abstract |
12:00 | UB10.8 | HIERARCHICAL ESL FAULT SIMULATION PACKAGE Authors: Somayeh Sadeghi-Kohan1, Arash Akhoundi1, Farnaz Forooghifar1, Elmira Karimi2, Mohammad Ghasemi1, Zahra Najafi1, Saba Amanollahi3 and Zain Navabi1 1University of Tehran, IR; 2Sharif University, IR; 3Shahid Beheshti University, IR Abstract |
12:00 | UB10.9 | PONG: APPLICATION FOR TEACHING CHIP DESIGN Authors: Armin Gruenewald, Matthias Mielke and Rainer Brück, University of Siegen, DE Abstract |
14:00 | End of session | |
15:30 | Coffee Break in Exhibition Hall Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme. |