Date: Wednesday 20 March 2013
Time: 14:30 - 16:00
Location / Room: Oisans

Organiser:
Ahmed Jerraya, CEA-LETI-MINATEC, FR

Chair:
Marc Duranton, CEA, FR

Co-Chair:
Ahmed Jerraya, CEA-LETI-MINATEC, FR

The evolution of the semiconductor industry is allowing intensive computing on a single chip through heterogeneous and homogeneous architectures. This increase in compute density on a single chip is both a threat and an opportunity for energy-efficiency. This Hot-Topic Session presents different many-core SoC approaches to improve energy-efficiency.

Time	Label	Presentation Title Authors
14:30	7.1.1	DEVELOPMENT OF LOW POWER MANY-CORE SOC FOR MULTIMEDIA APPLICATIONS Authors: Takashi Miyamori, Hui Xu, Takeshi Kodaka, Hiroyuki Usui, Toru Sano and Jun Tanabe, Toshiba, JP Abstract
14:50	7.1.2	SOC LOW-POWER PRACTICES FOR WIRELESS APPLICATIONS Authors: Nicolas Darbel and Stephane Lecomte, ST-Ericsson, FR Abstract
15:10	7.1.3	FUTURE LOW-POWER SOC Author: Koji Inoue, Kyushu University, JP Abstract
15:30	7.1.4	3D INTEGRATION FOR POWER-EFFICIENT COMPUTING Authors: Denis Dutoit, Eric Guthmuller and Ivan Miro-Panades, CEA-Leti, FR Abstract
16:00		End of session Coffee Break in Exhibition Hall Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.