Date: Wednesday 20 March 2013
Time: 11:00 - 12:30
Location / Room: Bayard

Organiser:
Krishnendu Chakrabarty, Duke University, US

Chair:
Mehdi Tahoori, Karlsruhe Institute of Technology, DE

Co-Chair:
Paul Pop, Technical University of Denmark, DK

In this hot topic session, the speakers will describe new, far-reaching design methods and test techniques that achieve energy efficiency and low defect escapes in massively integrated single-chip computing platforms. By integrating design, design automation, and test content, this session will provide a holistic view of multi-core systems to DATE attendees.

Time	Label	Presentation Title Authors
11:00	6.6.1	ENERGY-EFFICIENT MULTICORE CHIP DESIGN THROUGH CROSS-LAYER APPROACH Authors: Paul Wettin1, Jacob Murray1, Partha Pratim Pande1, Behrooz Shirazi1 and Amlan Ganguly2 1Washington State University, US; 2Rochester Institute of Technology, US Abstract
11:20	6.6.2	BREAKING THE ENERGY BARRIER IN FAULT-TOLERANT CACHES FOR MULTICORE SYSTEMS Authors: Paul Ampadu1, Meilin Zhang1 and Vladimir Stojanovic2 1University of Rochester, US; 2Massachusetts Institute of Technology, US Abstract
11:40	6.6.3	TESTING FOR SOCS WITH ADVANCED STATIC AND DYNAMIC POWER-MANAGEMENT CAPABILITIES Authors: Chrysovalantis Kavousianos1 and Krishnendu Chakrabarty2 1University of Ioannina, GR; 2Duke University, US Abstract
12:00	6.6.4	TOWARDS ADAPTIVE TEST OF MULTI-CORE RF SOCS Authors: Rajesh Mittal, Lakshmanan Balasubramanian, Chethan Kumar Y. B., V. R Devanathan, Mudasir Kawoosa and Rubin A. Parekhji, Texas Instruments, IN Abstract
12:30		End of session Lunch Break in Ecrins Sandwich lunch (Eat early for High-Performance Low-Power Computing - Energy Efficient Computing Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/7.0)