Date: Wednesday 20 March 2013
Time: 11:00 - 12:30
Location / Room: Belle-Etoile

Organisers:
Pierre-Emmanuel Gaillardon, EPFL, CH
Giovanni De Micheli, EPFL, CH

Chair:
Giovanni De Micheli, EPFL, CH

Co-Chair:
Ahmed Jerraya, CEA, LETI, Minatec, FR

As the semiconductor industry advances into the era of nanotechnology, the devices are expected to be scaled down to their physical and economic limits. These limitations require the industry to explore the use of novel materials and device structures able to replace the current CMOS transistors within the next few years. In this session, we elaborate on novel and emerging technologies, from advanced Silicon devices to carbon electronics, that can help pushing the Moore's Law beyond. We will detail the novel physical design techniques, architectural organizations and CAD tools identified to keep improving the performance of the computation structures, while maintaining an acceptable yield.

Time	Label	Presentation Title Authors
11:00	6.2.1	NEAR-THRESHOLD VOLTAGE DESIGN IN NANOSCALE CMOS Author: Vivek De, Intel, US Abstract
11:22	6.2.2	ULTRA-WIDE VOLTAGE RANGE DESIGNS IN FULLY-DEPLETED SILICON-ON-INSULATOR FET Authors: Edith Beigné1, Philippe Flatresse2, Bastien Giraud1, Jean-Philippe Noel2, Olivier Thomas1, Anuj Grover2, Thomas Benoist1, Fady Abouzeid2, Yvain Thonnart1, Bertrand Pelloux-Prayer2, Sébastien Bernard1, Sylvain Clerc2, Guillaume Moritz1, Philippe Roche2, Olivier Billoint1, Julien Le Coz2, Yves Maneglia1, Sylvain Engels2, Alexandre Valentian1 and Robin Wilson2 1CEA-Leti, Minatec, FR; 2STMicroelectronics, FR Abstract
11:45	6.2.3	CARBON NANOTUBE CIRCUITS: OPPORTUNITIES AND CHALLENGES Authors: Hai Wei, Max Shulaker, Gage Hills, Hong-Yu Chen, Chi-Shuen Lee, Luckshitha Liyanage, Jie Jerry Zhang, H.-S. Philip Wong and Subhasish Mitra, Stanford University, US Abstract
12:07	6.2.4	VERTICALLY-STACKED DOUBLE-GATE NANOWIRE FETS WITH CONTROLLABLE POLARITY: FROM DEVICES TO REGULAR ASICS Authors: Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici and Giovanni De Micheli, EPFL, CH Abstract
12:30		End of session Lunch Break in Ecrins Sandwich lunch (Eat early for High-Performance Low-Power Computing - Energy Efficient Computing Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/7.0)