Date: Tuesday 19 March 2013
Time: 14:30 - 16:00
Location / Room: Lesdigiueres (Exhibition Theatre)

Organiser:
Vikas Chandra, ARM, US

Chair:
Vikas Chandra, ARM, US

Co-Chair:
Kartik Mohanram, University of Pittsburgh, US

Complex SoCs of the future are subject to various sources of variability, reliability failures and design errors (logical or electrical) due to sheer design complexity, and marginal behaviors induced by uncertainties in manufacturing processes, temporal variability and operating conditions. In this session, we will cover this entire spectrum ranging from state-of-the-art techniques for manufacturability, variability and aging mitigation to effective post-silicon debug methods and everything in between

Time	Label	Presentation Title Authors
14:30	3.8.1	ROLE OF DESIGN IN MULTIPLE PATTERNING: TECHNOLOGY DEVELOPMENT, DESIGN ENABLEMENT AND PROCESS CONTROL Authors: Rani A. Ghaida1 and Puneet Gupta2 1GlobalFoundries, US; 2University of California, Los Angeles, US Abstract
15:00	3.8.2	OVERCOMING POST-SILICON VALIDATION CHALLENGES THROUGH QUICK ERROR DETECTION (QED) Authors: David Lin1, Ted Hong1, Yanjing Li1, Farzan Fallah1, Donald S. Gardner2, Nagib Hakim2 and Subhasish Mitra1 1Stanford University, US; 2Intel, US Abstract
15:30	3.8.3	STOCHASTIC DEGRADATION MODELING AND SIMULATION FOR ANALOG INTEGRATED CIRCUITS IN NANOMETER CMOS Authors: Georges Gielen and Elie Maricau, KU Leuven, BE Abstract
16:00		End of session Coffee Break in Exhibition Hall Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.