Date: Tuesday 19 March 2013
Time: 11:30 - 13:00
Location / Room: Lesdigiueres (Exhibition Theatre)
Organisers:
Wido Kruijtzer, Synopsys, NL
Luciano Lavagno, Politecnico di Torino, IT
Chair:
Wido Kruijtzer, Synopsys, NL
Co-Chair:
Luciano Lavagno, Politecnico di Torino, IT
System-on-Chip (SoC) integrators have to deal with more and more complexity during integration of their architectures. For cost and time-to-market reasons, SoCs tend to be architected as a set of coarse-grain subsystems for recognized system functions like audio, video, connectivity, modem, etc. Such subsystem solutions consist of multiple integrated hardware IP blocks together with associated software. Till recently IP subsystems were mostly adopted internally within SoC integrators and were not yet available from traditional IP companies. However, in 2012 multiple companies announced the availably of IP subsystem solutions. This special session will provide an update on the state-of-the art with regards to IP subsystems and review if IP subsystems indeed will be the way forward to boost productivity of SoC design.
Time | Label | Presentation Title Authors |
---|---|---|
11:30 | 2.8.1 | MODULAR SOC INTEGRATION WITH SUBSYSTEMS: THE AUDIO SUBSYSTEM CASE Authors: Pieter van der Wolf and Ruud Derwig, Synopsys, NL Abstract |
12:00 | 2.8.2 | CONFIGURABILITY IN IP SUBSYSTEMS: BASEBAND EXAMPLES Authors: Pierre-Xavier Thomas, Grant Martin, David Heine, Dennis Moolenaar and James Kim, Tensilica, US Abstract |
12:30 | 2.8.3 | CONFIGURABLE IO INTEGRATION TO REDUCE SYSTEM-ON-CHIP TIME TO MARKET: DDR, PCIE EXAMPLES Authors: Frank Martin and Peter Bennett, Cadence, UK Abstract |
12:45 | 2.8.4 | HIGH-PERFORMANCE IMAGING SUBSYSTEMS AND THEIR INTEGRATION IN MOBILE DEVICES Authors: Menno Lindwer1 and Mark Ruvald Pedersen2 1Intel, NL; 2Intel, DK Abstract |
13:00 | End of session Lunch Break in Auditorium Dauphine (Lunch and Learn Session) and Ecrins Sandwich lunch in both locations (Lunch and Learn Session Sponsored by Mentor Graphics: "Grenoble Ecosystem to Provide Semiconductor Alternative Process for Advanced CMOS - 1300-1400 hrs; http://www.date-conference.com/conference/session/3.0) |