Date: Thursday 21 March 2013
Time: 16:00 - 17:30
Location / Room: Bayard

Chair:
Tiziano Villa, University of Verona, IT

Co-Chair:
Georges Gielen, Katholieke Universiteit Leuven, BE

The first two papers of this session address the optimization of clock distribution. The first paper deals with clock-skew scheduling combined with clock-gating. The second paper addresses the power reduction of the clock-tree using multi-bit flip-flops. The last two papers of this session address the synthesis of analogue circuits, dealing with hierarchy, layout issues, and non-CMOS technologies.

Time	Label	Presentation Title Authors
16:00	12.6.1	CO-SYNTHESIS OF DATA PATHS AND CLOCK CONTROL PATHS FOR MINIMUM-PERIOD CLOCK GATING Authors: Wen-Pin Tu, Shih-Hsu Huang and Chun-Hua Cheng, Chung Yuan Christian University, TW Abstract
16:30	12.6.2	SLACK BUDGETING AND SLACK-TO-ENGTH CONVERTING FOR MULTI-BIT FLIP-FLOP MERGING Authors: Chia-Chieh Lu and Rung-Bin Lin, Yuan Ze University, TW Abstract
16:45	12.6.3	AREA OPTIMIZATION ON FIXED ANALOG FLOORPLANS USING CONVEX AREA FUNCTIONS Authors: Ahmet Unutulmaz1, Gunhan Dundar1 and Francisco Fernandez2 1Bogazici University, TR; 2IMSE-CNM, CSIC and University of Sevilla, ES Abstract
17:00	12.6.4	PAGE: PARALLEL AGILE GENETIC EXPLORATION TOWARD UTMOST PERFORMANCE FOR ANALOG CIRCUIT DESIGN Authors: Po-Cheng Pan, Hung-Ming Chen and Chien-Chih Lin, National Chiao Tung University, TW Abstract
17:30		End of session