12.5 Emerging Technology Architectures for Energy-Efficient Memories
Date: Thursday 21 March 2013
Time: 16:00 - 17:30
Location / Room: Meije
Chair:
Marisa López-Vallejo, Universidad Politecnica Madrid, ES
Co-Chair:
Alberto Macii, Politecnico di Torino, IT
This session presents three papers targeting energy efficiency in memory architectures. The first paper presents a new hybrid DRAM/MRAM approach, the second paper describes a sensitivity analysis to simulate SRAMs dynamic write-ability under process variations and the third one reports how domain wall memories can be used for design on-chip cache hierarchies.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 16:00 | 12.5.1 | D-MRAM CACHE: ENHANCING ENERGY EFFICIENCY WITH 3T-1MTJ DRAM / MRAM HYBRID MEMORY Authors: Hiroki Noguchi1, Kumiko Nomura1, Keiko Abe1, Shinobu Fujita1, Eishi Arima2, Kyundong Kim2, Takashi Nakada2, Shinobu Miwa2 and Hiroshi Nakamura2 1Toshiba, JP; 2University of Tokyo, JP Abstract |
| 16:30 | 12.5.2 | LEVERAGING SENSITIVITY ANALYSIS FOR FAST, ACCURATE ESTIMATION OF SRAM DYNAMIC WRITE VMIN Authors: James Boley1, Vikas Chandra2, Rob Aitken2 and Benton Calhoun1 1University of Virginia, US; 2ARM, US Abstract |
| 17:00 | 12.5.3 | DWM-TAPESTRI - AN ENERGY EFFICIENT ALL-SPIN CACHE USING DOMAIN WALL SHIFT BASED WRITES Authors: Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy and Anand Raghunathan, Purdue University, US Abstract |
| 17:30 | End of session | |
