Date: Thursday 21 March 2013
Time: 11:00 - 12:30
Location / Room: Belle-Etoile

Organiser:
Franco Fummi, University of Verona, IT

Chair:
Franco Fummi, University of Verona, IT

Co-Chair:
Florian Letombe, SpringSoft, FR

General purpose graphics processing units (GP-GPUs) have recently been explored as a new computing paradigm for accelerating computation intensive EDA applications. Such many-core architectures have been applied for (i) accelerating both logic and fault simulation of HDL designs, (ii) accelerating simulation of such designs described both at RTL and Gate level, (iii) accelerating SystemC simulation. This embedded tutorial presents a comprehensive analysis of the best results obtained by adopting GP-GPUs in all these EDA applications.

Time	Label	Presentation Title Authors
11:00	10.2.1	ON THE USE OF GP-GPUS FOR ACCELERATING LOGIC SIMULATION Authors: Valeria Bertacco and Debapriya Chatterjee, University of Michigan, US Abstract
11:30	10.2.2	ACCELERATING RTL SIMULATION WITH GP-GPUS: CUDA VS. OPENCL Authors: Nicola Bombieri and Sara Vinco, University of Verona, IT Abstract
12:00	10.2.3	PARALLELIZING SYSTEMC SIMULATIONS ACROSS CPUS AND GPUS Author: Hiren Patel, University of Waterloo, CA Abstract
12:30		End of session Lunch Break in Ecrins Buffet lunch (Eat early for Smart Cities and Communities Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/11.0)