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A.1 Opening Session

Date: Monday 18 March 2013
Time: 08:15 - 08:30
Location / Room:

TimeLabelPresentation Title
Authors
08:30End of session
11:00Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

A.2 Simulation and Circuit Design

Date: Monday 18 March 2013
Time: 08:30 - 09:30
Location / Room:

TimeLabelPresentation Title
Authors
08:30A.2.1EDA BEYOND ELECTRONICS: ANECDOTAL EVIDENCE IN SYSTEMS BIOLOGY, MRI OPTIMIZATION, AND ELECTRIC VEHICLE SIMULATION
Author:
Jacob White, MIT, US
Abstract
09:00A.2.2PHASE LOGIC USING SELF-SUSTAINING NONLINEAR OSCILLATORS
Author:
Jaijeet Roychowdhury, University of California, Berkeley, US
Abstract
09:30End of session
11:00Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

C.1 Session 1

Date: Monday 18 March 2013
Time: 09:00 - 11:00
Location / Room:

TimeLabelPresentation Title
Authors
09:00C.1.1INTRODUCTION, MOTIVATION AND BIG PICTURE
Author:
Rudy Lauwereins, IMEC, BE
Abstract
11:00End of session
Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

A.3 Logic Synthesis and Computer Architecture

Date: Monday 18 March 2013
Time: 09:30 - 11:00
Location / Room:

TimeLabelPresentation Title
Authors
09:30A.3.1TOWARDS THE UNIFICATION OF SYNTHESIS AND VERIFICATION IN LOGIC AND ARCHITECTURAL DESIGN
Author:
Masahiro Fujita, University of Tokyo, JP
Abstract
10:00A.3.2FROM 2-LEVEL TO ARCHITECTURAL SYNTHESIS: A LONG TRIP FOR DESIGN AUTOMATION
Author:
Jordi Cortadella, Universitat Politècnica de Catalunya, ES
Abstract
10:30A.3.3DECOMPOSITION OF BOOLEAN EXPRESSIONS 30 YEARS AFTER THE FIRST ALGEBRAIC FACTORING ALGORITHM
Author:
Victor Kravets, IBM, US
Abstract
11:00End of session
Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

B.1 Session 1

Date: Monday 18 March 2013
Time: 09:30 - 11:00
Location / Room:

TimeLabelPresentation Title
Authors
09:30B.1.1INTRODUCTION AND TUTORIAL OVERVIEW
Author:
Frank Oppenheimer, OFFIS, DE
Abstract
10:00B.1.2AN MDD METHODOLOGY FOR SPECIFICATION AND PERFORMANCE ESTIMATION OF EMBEDDED SYSTEMS
Author:
Eugenio Villar, Universidad de Cantabria, ES
Abstract
11:00End of session
Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

D1.1 Session 1

Date: Monday 18 March 2013
Time: 09:30 - 11:00
Location / Room:

TimeLabelPresentation Title
Authors
09:30D1.1.1TECHNOLOGY OVERVIEW
Author:
Krishnendu Chakrabarty, Duke University, US
Abstract
10:15D1.1.2FLUIDIC SYNTHESIS METHODS
Author:
Tsung-Yi Ho, National Cheng Kung Univ., TW
Abstract
11:00End of session
Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

E1.1 Session1

Date: Monday 18 March 2013
Time: 09:30 - 11:00
Location / Room:

TimeLabelPresentation Title
Authors
09:30E1.1.1INTRODUCTION TO ABV AND PSL
Author:
Graziano Pravadelli, Università di Verona, IT
Abstract
10:00E1.1.2ABV FOR SOC
Author:
Masahiro Fujita, University of Tokyo, JP
Abstract
11:00End of session
Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

F.1 Session 1

Date: Monday 18 March 2013
Time: 09:30 - 11:00
Location / Room:

TimeLabelPresentation Title
Authors
09:30POST-SILICON BUGS AND INDUSTRY TOOLS
Authors:
Rand Gray1 and Wisam Kadry2
1Intel Corp, US; 2IBM, IL
Abstract
11:00End of session
Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

G.1 Session 1

Date: Monday 18 March 2013
Time: 09:30 - 11:00
Location / Room:

TimeLabelPresentation Title
Authors
09:00G.1.1INTRODUCTION AND MOTIVATION
Author:
Saibal Mukhopadhyay, Georgia Institute of Technology, US
Abstract
10:15G.1.2ADAPTIVE LOGIC CIRCUITS
Author:
Saibal Mukhopadhyay, Georgia Institute of Technology, US
Abstract
11:00End of session
Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

H1.1 Session 1

Date: Monday 18 March 2013
Time: 09:30 - 11:00
Location / Room:

TimeLabelPresentation Title
Authors
09:30TRENDS, AND REVIEW OF IEEE STANDARDS
Author:
Stephen Sunter, Mentor Graphics, US
Abstract
11:00End of session
Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

A.4 Physical Design and Timing Analysis

Date: Monday 18 March 2013
Time: 11:00 - 12:00
Location / Room:

TimeLabelPresentation Title
Authors
11:00A.4.1SPACE (AND PHYSICAL DESIGN): THE FINAL FRONTIER FOR VLSI
Author:
Igor Markov, University of Michigan, US
Abstract
11:30A.4.2TECHNOLOGY-BASED LOGIC TRANSFORMS
Author:
Rajeev Murgai, Synopsys, IN
Abstract
12:00End of session
Lunch Break in Ecrins
Buffet meal

B Coffee Break

Date: Monday 18 March 2013
Time: 11:00 - 11:30
Location / Room: Salle de Reception (Pelvoux)

Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

TimeLabelPresentation Title
Authors
11:30End of session
12:00Lunch Break in Ecrins
Buffet meal

C Coffee Break

Date: Monday 18 March 2013
Time: 11:00 - 11:30
Location / Room: Salle de Reception (Pelvoux)

Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

TimeLabelPresentation Title
Authors
11:30End of session
12:00Lunch Break in Ecrins
Buffet meal

D1 Coffee Break

Date: Monday 18 March 2013
Time: 11:00 - 11:30
Location / Room: Salle de Reception (Pelvoux)

Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

TimeLabelPresentation Title
Authors
11:30End of session
12:00Lunch Break in Ecrins
Buffet meal

E1 Coffee Break

Date: Monday 18 March 2013
Time: 11:00 - 11:30
Location / Room: Salle de Reception (Pelvoux)

Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

TimeLabelPresentation Title
Authors
11:30End of session
12:00Lunch Break in Ecrins
Buffet meal

F Coffee Break

Date: Monday 18 March 2013
Time: 11:00 - 11:30
Location / Room: Salle de Reception (Pelvoux)

Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

TimeLabelPresentation Title
Authors
11:30End of session
12:00Lunch Break in Ecrins
Buffet meal

G Coffee Break

Date: Monday 18 March 2013
Time: 11:00 - 11:30
Location / Room: Salle de Reception (Pelvoux)

Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

TimeLabelPresentation Title
Authors
11:30End of session
12:00Lunch Break in Ecrins
Buffet meal

H1 Coffee Break

Date: Monday 18 March 2013
Time: 11:00 - 11:30
Location / Room: Salle de Reception (Pelvoux)

Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

TimeLabelPresentation Title
Authors
11:30End of session
12:00Lunch Break in Ecrins
Buffet meal

B.2 Session 2

Date: Monday 18 March 2013
Time: 11:30 - 13:00
Location / Room:

TimeLabelPresentation Title
Authors
11:30B.2.1VIRTUAL PLATFORM GENERATION, INTEGRATION AND EXTENSION OF EXTRA-FUNCTIONAL PROPERTIES
Author:
Emmanuel Vaumorin, Magillem, FR
Abstract
12:00B.2.2INDUSTRIAL EXPERIENCE REPORT FOR MODEL-BASED DESIGN IN SPACE/AEROSPACE APPLICATIONS (DEMO)
Author:
Francisco Ferrero, GMV AD, ES
Abstract
13:00End of session
Lunch Break in Ecrins
Buffet meal

C.2 Session 2

Date: Monday 18 March 2013
Time: 11:30 - 13:00
Location / Room:

TimeLabelPresentation Title
Authors
11:30C.2.1SURVEY OF BIOSENSORS FOR MEDICAL APPLICATIONS
Author:
Sven Ingebrandt, University of Kaiserslautern, DE
Abstract
12:15C.2.2BIOSENSOR INTEGRATION
Author:
Carlotta Guiducci, École Polytechnique Fédérale de Lausanne, CH
Abstract
13:00End of session
Lunch Break in Ecrins
Buffet meal

D1.2 Session 2

Date: Monday 18 March 2013
Time: 11:30 - 13:00
Location / Room:

TimeLabelPresentation Title
Authors
11:30D1.2.1CHIP DESIGN
Author:
Tsung-Yi Ho, National Cheng Kung Univ., TW
Abstract
12:00D1.2.2CYBERPHYSICAL INTEGRATION
Author:
Krishnendu Chakrabarty, Duke University, US
Abstract
12:30D1.2.3DYNAMIC RECONFIGURATION
Author:
Krishnendu Chakrabarty, Duke University, US
Abstract
13:00End of session
Lunch Break in Ecrins
Buffet meal

E1.2 Session 2

Date: Monday 18 March 2013
Time: 11:30 - 13:00
Location / Room:

TimeLabelPresentation Title
Authors
11:30E1.2.1DYNAMIC ABV FOR EMBEDDED SW
Author:
Giuseppe Di Guglielmo, Columbia University, US
Abstract
12:30E1.2.2ABV AND THE IEC 60730 SAFETY STANDARD
Author:
Cristina Marconcini, STM Product, IT
Abstract
13:00End of session
Lunch Break in Ecrins
Buffet meal

F.2 Session 2

Date: Monday 18 March 2013
Time: 11:30 - 13:00
Location / Room:

TimeLabelPresentation Title
Authors
11:30POST-SILICON MONITORING INFRASTRUCTURES
Authors:
Valeria Bertacco1 and Sharad Malik2
1University of Michigan, US; 2Princeton University, US
Abstract
13:00End of session
Lunch Break in Ecrins
Buffet meal

G.2 Session 2

Date: Monday 18 March 2013
Time: 11:30 - 13:00
Location / Room:

TimeLabelPresentation Title
Authors
11:30ADAPTIVE SRAM CIRCUITS
Author:
Arijit Raychowdhury, Georgia Institute of Technology, US
Abstract
13:00End of session
Lunch Break in Ecrins
Buffet meal

H1.2 Session 2

Date: Monday 18 March 2013
Time: 11:30 - 13:00
Location / Room:

TimeLabelPresentation Title
Authors
11:30BIST PRINCIPLES, AND TECHNIQUES FOR NEW DFT
Author:
Stephen Sunter, Mentor Graphics, US
Abstract
13:00End of session
Lunch Break in Ecrins
Buffet meal

A Lunch Break

Date: Monday 18 March 2013
Time: 12:00 - 13:00
Location / Room: Ecrins

Buffet meal

TimeLabelPresentation Title
Authors
13:00End of session
Lunch Break in Ecrins
Buffet meal

A.5 Formal Verification and Equivalence Checking

Date: Monday 18 March 2013
Time: 13:00 - 14:00
Location / Room:

TimeLabelPresentation Title
Authors
13:00A.5.1COMBINING ALGORITHMS TO SOLVE INTRACTABLE PROBLEMS
Author:
Ken McMillan, Microsoft, US
Abstract
13:30A.5.2INTEGRATING INDUCTION AND DEDUCTION FOR VERIFICATION AND SYNTHESIS
Author:
Sanjit Seshia, University of California, Berkeley, US
Abstract
14:00End of session
16:00Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

B Lunch Break

Date: Monday 18 March 2013
Time: 13:00 - 14:30
Location / Room: Ecrins

Buffet meal

TimeLabelPresentation Title
Authors
14:30End of session
16:00Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

C Lunch Break

Date: Monday 18 March 2013
Time: 13:00 - 14:30
Location / Room: Ecrins

Buffet meal

TimeLabelPresentation Title
Authors
14:30End of session
16:00Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

D1 Lunch Break

Date: Monday 18 March 2013
Time: 13:00 - 14:30
Location / Room: Ecrins

Buffet meal

TimeLabelPresentation Title
Authors
14:30End of session
16:00Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

D2 Lunch Break

Date: Monday 18 March 2013
Time: 13:00 - 14:30
Location / Room: Ecrins

Buffet meal

TimeLabelPresentation Title
Authors
14:30End of session
16:00Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

E1 Lunch Break

Date: Monday 18 March 2013
Time: 13:00 - 14:30
Location / Room: Ecrins

Buffet meal

TimeLabelPresentation Title
Authors
14:30End of session
16:00Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

E2 Lunch Break

Date: Monday 18 March 2013
Time: 13:00 - 14:30
Location / Room: Ecrins

Buffet meal

TimeLabelPresentation Title
Authors
14:30End of session
16:00Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

F Lunch Break

Date: Monday 18 March 2013
Time: 13:00 - 14:30
Location / Room: Ecrins

Buffet meal

TimeLabelPresentation Title
Authors
14:30End of session
16:00Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

G Lunch Break

Date: Monday 18 March 2013
Time: 13:00 - 14:30
Location / Room: Ecrins

Buffet meal

TimeLabelPresentation Title
Authors
14:30End of session
16:00Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

H1 Lunch Break

Date: Monday 18 March 2013
Time: 13:00 - 14:30
Location / Room: Ecrins

Buffet meal

TimeLabelPresentation Title
Authors
14:30End of session
16:00Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

H2 Lunch Break

Date: Monday 18 March 2013
Time: 13:00 - 14:30
Location / Room: Ecrins

Buffet meal

TimeLabelPresentation Title
Authors
14:30End of session
16:00Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

A.6 New Frontiers of EDA

Date: Monday 18 March 2013
Time: 14:00 - 15:00
Location / Room:

TimeLabelPresentation Title
Authors
14:00A.6.1NEW FRONTIERS OF LOGIC DESIGN TOOLS
Author:
Giovanni De Micheli, Ecole Polyt. de Lausanne, CH
Abstract
14:30A.6.2BIO-DESIGN AUTOMATION: DESIGNING GENETIC CIRCUITS WITH EDA PRINCIPLES
Author:
Douglas Densmore, Boston University, US
Abstract
15:00End of session
16:00Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

B.3 Session 3

Date: Monday 18 March 2013
Time: 14:30 - 16:00
Location / Room:

TimeLabelPresentation Title
Authors
14:30B.3.1FROM RTL IP TO FUNCTIONAL SYSTEM-LEVEL MODELS WITH EXTRA-FUNCTIONAL PROPERTIES
Author:
Davide Quaglia, EDALab, IT
Abstract
15:15B.3.2HIGH-LEVEL SYNTHESIS-BASED HARDWARE POWER AND TIMING ESTIMATION
Author:
Philipp A. Hartmann, OFFIS, DE
Abstract
16:00End of session
Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

C.3 Session 3

Date: Monday 18 March 2013
Time: 14:30 - 16:00
Location / Room:

TimeLabelPresentation Title
Authors
14:30C.3.1MEMS FOR HEALTH APPLICATIONS
Author:
Benedetto Vigna, STMicroelectronics, IT
Abstract
16:00End of session
Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

D2.1 Session 1

Date: Monday 18 March 2013
Time: 14:30 - 16:00
Location / Room:

TimeLabelPresentation Title
Authors
15:00D2.1.2MALICIOUS MODIFICATIONS (HARDWARE TROJANS) TO DESIGNS AND COUNTERFEIT ICS
Author:
Yiorgos Makris, University of Texas at Dallas, US
Abstract
14:30D2.1.1INTRODUCTION, MOTIVATION, HARDWARE SECURITY PRIMITIVES
Author:
Ramesh Karri, Polytechnic Institute of New York University, US
Abstract
16:00End of session
Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

E2.1 Session 1

Date: Monday 18 March 2013
Time: 14:30 - 14:45
Location / Room:

TimeLabelPresentation Title
Authors
14:30E2.1.1INTRODUCTION AND ENVISIONED DESIGN FLOW
Author:
Robert Wille, University of Bremen, DE
Abstract
14:45E2.1.2NATURAL LANGUAGE PROCESSING
Author:
Ian G. Harris, University of California, Irvine, US
Abstract
15:30E2.1.3DERIVING FORMAL SPECIFICATIONS THROUGH NLP
Author:
Rolf Drechsler, DFKI GmbH, DE
Abstract
14:45End of session
16:00Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

F.3 Session 3

Date: Monday 18 March 2013
Time: 14:30 - 16:00
Location / Room:

TimeLabelPresentation Title
Authors
14:30BUG LOCALIZATION. MICROPROCESSOR'S SOLUTIONS
Authors:
Valeria Bertacco1 and Sharad Malik2
1University of Michigan, US; 2Princeton University, US
Abstract
16:00End of session
Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

G.3 Session 3

Date: Monday 18 March 2013
Time: 14:30 - 16:00
Location / Room:

TimeLabelPresentation Title
Authors
14:30ADAPTIVE ARCHITECTURE
Author:
Sudhakar Yalamanchili, Georgia Institute of Technology, US
Abstract
16:00End of session
Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

H2.1 Session 1

Date: Monday 18 March 2013
Time: 14:30 - 16:00
Location / Room:

TimeLabelPresentation Title
Authors
14:30H2.1.1INTRODUCTION AND BACKGROUND
Author:
Rob Aitken, ARM, US
Abstract
15:00H2.1.2YIELD AND FAB METROLOGY
Author:
Rob Aitken, ARM, US
Abstract
15:30H2.1.3DFM/Y - DESIGN FOR MANUFACTURABILITY AND YIELD
Author:
Rob Aitken, ARM, US
Abstract
15:30H2.1.4VARIABILITY AND DFV
Author:
Rob Aitken, ARM, US
Abstract
16:00End of session
Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

A.7 Formal Models

Date: Monday 18 March 2013
Time: 15:00 - 16:00
Location / Room:

TimeLabelPresentation Title
Authors
15:00A.7.1ERROR LOCALIZATION USING MAXIMAL SATISFIABILITY
Author:
Rupak Majumdar, University of California, Los Angeles, US
Abstract
15:30A.7.2THE UNKNOWN COMPONENT PROBLEM
Author:
Alexandre Petrenko, CRIM, CA
Abstract
16:00End of session
Coffee Break in Salle de Reception (Pelvoux)
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

A.8 System Design

Date: Monday 18 March 2013
Time: 16:00 - 17:00
Location / Room:

TimeLabelPresentation Title
Authors
16:00A.8.1FROM LATENCY-INSENSITIVE TO COMMUNICATION-BASED SYSTEM- LEVEL DESIGN
Author:
Luca Carloni, Columbia University, US
Abstract
16:30A.8.2EDA: THE LAST 40 YEARS AND THE NEXT 20 YEARS
Author:
Alberto Sangiovanni-Vincentelli, University of California, Berkeley, US
Abstract
17:00End of session
18:00Welcome Reception in Adjacent to the Conference Registration Desk
Wine (The EDAA/ACM PhD Forum will take place from 1900 - 2100 hrs in the Salle de Reception)

B Coffee Break

Date: Monday 18 March 2013
Time: 16:00 - 16:30
Location / Room: Salle de Reception (Pelvoux)

Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

TimeLabelPresentation Title
Authors
16:30End of session
18:00Welcome Reception in Adjacent to the Conference Registration Desk
Wine (The EDAA/ACM PhD Forum will take place from 1900 - 2100 hrs in the Salle de Reception)

C Coffee Break

Date: Monday 18 March 2013
Time: 16:00 - 16:30
Location / Room: Salle de Reception (Pelvoux)

Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

TimeLabelPresentation Title
Authors
16:30End of session
18:00Welcome Reception in Adjacent to the Conference Registration Desk
Wine (The EDAA/ACM PhD Forum will take place from 1900 - 2100 hrs in the Salle de Reception)

D2 Coffee Break

Date: Monday 18 March 2013
Time: 16:00 - 16:30
Location / Room: Salle de Reception (Pelvoux)

Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

TimeLabelPresentation Title
Authors
16:30End of session
18:00Welcome Reception in Adjacent to the Conference Registration Desk
Wine (The EDAA/ACM PhD Forum will take place from 1900 - 2100 hrs in the Salle de Reception)

E2 Coffee Break

Date: Monday 18 March 2013
Time: 16:00 - 16:30
Location / Room: Salle de Reception (Pelvoux)

Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

TimeLabelPresentation Title
Authors
16:30End of session
18:00Welcome Reception in Adjacent to the Conference Registration Desk
Wine (The EDAA/ACM PhD Forum will take place from 1900 - 2100 hrs in the Salle de Reception)

F Coffee Break

Date: Monday 18 March 2013
Time: 16:00 - 16:30
Location / Room: Salle de Reception (Pelvoux)

Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

TimeLabelPresentation Title
Authors
16:30End of session
18:00Welcome Reception in Adjacent to the Conference Registration Desk
Wine (The EDAA/ACM PhD Forum will take place from 1900 - 2100 hrs in the Salle de Reception)

G Coffee Break

Date: Monday 18 March 2013
Time: 16:00 - 16:30
Location / Room: Salle de Reception (Pelvoux)

Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

TimeLabelPresentation Title
Authors
16:30End of session
18:00Welcome Reception in Adjacent to the Conference Registration Desk
Wine (The EDAA/ACM PhD Forum will take place from 1900 - 2100 hrs in the Salle de Reception)

H2 Coffee Break

Date: Monday 18 March 2013
Time: 16:00 - 16:30
Location / Room: Salle de Reception (Pelvoux)

Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

TimeLabelPresentation Title
Authors
16:30End of session
18:00Welcome Reception in Adjacent to the Conference Registration Desk
Wine (The EDAA/ACM PhD Forum will take place from 1900 - 2100 hrs in the Salle de Reception)

B.4 Session 4

Date: Monday 18 March 2013
Time: 16:30 - 18:00
Location / Room:

TimeLabelPresentation Title
Authors
16:30B.4.1SOFTWARE POWER AND TIMING ESTIMATION
Author:
Carlo Brandolese, Politecnico di Milano, IT
Abstract
17:00B.4.2NETWORK-AWARE DESIGN-SPACE EXPLORATION OF A POWER-EFFICIENT EMBEDDED APPLICATION (DEMO)
Author:
Sara Bocchio, STMicroelectronics, IT
Abstract
17:30B.4.3SUMMARY AND CLOSING REMARKS
Author:
Frank Oppenheimer, OFFIS, DE
Abstract
18:00End of session
Welcome Reception in Adjacent to the Conference Registration Desk
Wine (The EDAA/ACM PhD Forum will take place from 1900 - 2100 hrs in the Salle de Reception)

C.4 Session 4

Date: Monday 18 March 2013
Time: 16:30 - 18:00
Location / Room:

TimeLabelPresentation Title
Authors
16:30C.4.1SYSTEM DESIGN ISSUES IN E-HEALTH APPLICATIONS
Author:
Wayne Burleson, University of Massachusetts Amherst, US
Abstract
17:15C.4.2CASE STUDIES AND CONCLUSIONS
Author:
Giovanni De Micheli, École Polytechnique Fédérale de Lausanne, CH
Abstract
18:00End of session
Welcome Reception in Adjacent to the Conference Registration Desk
Wine (The EDAA/ACM PhD Forum will take place from 1900 - 2100 hrs in the Salle de Reception)

D2.2 Session 2

Date: Monday 18 March 2013
Time: 16:30 - 18:00
Location / Room:

TimeLabelPresentation Title
Authors
16:30D2.2.1IC REVERSE ENGINEERING, OVERBUILDING AND IP PIRACY
Author:
Ozgur Sinanoglu, New York University Abu Dhabi, AE
Abstract
17:30D2.2.2DESIGN FOR TEST VULNERABILITIES AND COUNTERMEASURES
Author:
Ramesh Karri, Polytechnic Institute of New York University, US
Abstract
18:00End of session
Welcome Reception in Adjacent to the Conference Registration Desk
Wine (The EDAA/ACM PhD Forum will take place from 1900 - 2100 hrs in the Salle de Reception)

E2.2 Session 2

Date: Monday 18 March 2013
Time: 16:30 - 18:00
Location / Room:

TimeLabelPresentation Title
Authors
16:30E2.2.1VERIFICATION OF FORMAL SPECIFICATIONS
Author:
Robert Wille, University of Bremen, DE
Abstract
17:00E2.2.2CODE GENERATION
Authors:
Wolfgang Ecker1 and Rainer Findenig2
1Infineon Technologies, DE; 2Intel Mobile Communications, AT
Abstract
17:45E2.2.3CONCLUSION AND OPEN RESEARCH QUESTIONS
Author:
Rolf Drechsler, DFKI GmbH, DE
Abstract
18:00End of session
Welcome Reception in Adjacent to the Conference Registration Desk
Wine (The EDAA/ACM PhD Forum will take place from 1900 - 2100 hrs in the Salle de Reception)

F.4 Session 4

Date: Monday 18 March 2013
Time: 16:30 - 18:00
Location / Room:

TimeLabelPresentation Title
Authors
16:30POST-SILICON METHODOLOGIES IN THE INDUSTRY
Authors:
Rand Gray1 and Wisam Kadry2
1Intel Corp, US; 2IBM, IL
Abstract
18:00End of session
Welcome Reception in Adjacent to the Conference Registration Desk
Wine (The EDAA/ACM PhD Forum will take place from 1900 - 2100 hrs in the Salle de Reception)

G.4 Session 4

Date: Monday 18 March 2013
Time: 16:30 - 18:00
Location / Room:

TimeLabelPresentation Title
Authors
16:00G.7.1ADAPTIVE WIRELESS SYSTEMS
Author:
Abhijit Chatterjee, Georgia Institute of Technology, US
Abstract
17:15G.7.2CONCLUSION AND DISCUSSION
Authors:
Saibal Mukhopadhyay, Abhijit Chatterjee, Sudhakar Yalamanchili and Arijit Raychowdhury, Georgia Institute of Technology, US
Abstract
18:00End of session
Welcome Reception in Adjacent to the Conference Registration Desk
Wine (The EDAA/ACM PhD Forum will take place from 1900 - 2100 hrs in the Salle de Reception)

H2.2 Session 2

Date: Monday 18 March 2013
Time: 16:30 - 18:00
Location / Room:

TimeLabelPresentation Title
Authors
16:30H2.2.1DFT / TEST AND THE LINK TO MANUFACTURABILITY
Author:
Rob Aitken, ARM, US
Abstract
16:55H2.2.2DIAGNOSIS AND THE FEEDBACK LOOP
Author:
Rob Aitken, ARM, US
Abstract
17:20H2.2.3RELIABILITY
Author:
Rob Aitken, ARM, US
Abstract
17:45H2.2.4PUTTING IT ALL TOGETHER
Abstract
18:00End of session
Welcome Reception in Adjacent to the Conference Registration Desk
Wine (The EDAA/ACM PhD Forum will take place from 1900 - 2100 hrs in the Salle de Reception)

A.9 Conclusions

Date: Monday 18 March 2013
Time: 17:00 - 17:15
Location / Room:

Moderators:
Robert Brayton, University of California at Berkeley, US
Tiziano Villa, Università di Verona, IT

TimeLabelPresentation Title
Authors
17:15End of session
18:00Welcome Reception in Adjacent to the Conference Registration Desk
Wine (The EDAA/ACM PhD Forum will take place from 1900 - 2100 hrs in the Salle de Reception)

1.1 Plenary: Opening and Keynote

Date: Tuesday 19 March 2013
Time: 08:30 - 10:30
Location / Room: Auditorium Dauphine

Co-Chair:
Enrico Macii, Politecnico di Torino, IT

TimeLabelPresentation Title
Authors
09:00DATE 2012 BEST PAPER AWARD
Author:
Zebo Peng, Linköping University, SE
Abstract: The DATE 2012 Best Paper Award is given for "Compositional System-Level Design Exploration with Planning of High-Level Synthesis", by Hung-Yi Liu, Michele Petracca, and Luca P. Carloni, Columbia University, US.
09:02DATE 2013 BEST PAPER AWARDS
Author:
Giovanni De Micheli, EPFL, CH
08:301.1.1OPENING REMARKS
Authors:
Enrico Macii1 and Erik Jan Marinissen2
1Politecnico di Torino, IT; 2IMEC, BE
09:121.1.2PRESENTATION OF DISTINGUISHED AWARDS
Abstract: Find details here
09:201.1.3SMART SYSTEMS FOR INTERNET OF THINGS
Author:
Benedetto Vigna, STMicroelectronics, IT
Abstract: Sensors add intelligence to systems which represent a broad class of devices incorporating functionalities like sensing, actuation, and control. They are the core of smart components and subsystems; then, the challenge in the realization of such smart systems goes beyond the design of the individual components and subsystems and consists of accommodating a multitude of functionalities, technologies, and materials to play a key role to augment our daily life.
09:551.1.4CREATING A SUSTAINABLE INFORMATION AND COMMUNICATION INFRASTRUCTURE
Author:
Massoud Pedram, University of Southern California, US
Abstract: Modern society's dependence on information and communication infrastructure (ICI) is so deeply entrenched that it should be treated on par with other critical lifelines of our existence, such as water and electricity. As is the case with any true lifeline, ICI must be reliable, affordable, and sustainable. Meeting these requirements (especially sustainability) is a continued critical challenge, which will be the focus of my talk. More precisely, I will provide an overview of information and communication technology trends in light of various societal and environmental mandates followed by a review of technologies, systems, and hardware/software solutions required to create a sustainable ICI.
10:30End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

UB01 Session 1

Date: Tuesday 19 March 2013
Time: 10:30 - 12:30
Location / Room: Booth 46, Exhibition

TimeLabelPresentation Title
Authors
10:30UB01.1MICROTESK: ADVANCED TEST PROGRAM GENERATOR FOR MICROPROCESSORS
Authors:
Andrei Tatarnikov and Alexander Kamkin, Institute for System Programming of the Russian Academy of Sciences (ISP RAS), RU
Abstract
10:30UB01.2THE MATISSE MATLAB COMPILER
Authors:
João Cardoso1, João Bispo1, Pedro Pinto1, Ricardo Nobre1, Tiago Carvalho1 and Pedro Diniz2
1University of Porto, PT; 2INESC-ID, PT
Abstract
10:30UB01.3EDKDSP: REPROGRAMMABLE FLOATING POINT ACCELERATORS ON KINTEX FPGA WITH HDMI
Author:
Jiri Kadlec, UTIA AV CR v.v.i., CZ
Abstract
10:30UB01.4FPGA-BASED IN SYSTEM MULTIPLE LRU CACHE SIMULATION
Authors:
Josef Schneider, Jorgen Peddersen and Sridevan Parameswaran, University of New South Wales, AU
Abstract
10:30UB01.5ID.FIX: A SOFTWARE INFRASTRUCTURE FOR THE DESIGN OF EMBEDDED SYSTEMS USING FIXED-POINT ARITHMETIC
Authors:
Olivier Sentieys1, Daniel Ménard2 and Romuald Rocher3
1INRIA, FR; 2INSA Rennes, FR; 3University of Rennes 1, FR
Abstract
10:30UB01.6ASAP: AN OPEN-SOURCE FRAMEWORK FOR EARLY VALIDATION OF HETEROGENEOUS RECONFIGURABLE SYSTEMS
Authors:
Christian Pilato, Alessandro Antonio Nacci, Gianluca Durelli, Riccardo Cattaneo, Marco Domenico Santambrogio and Donatella Sciuto, Politecnico di Milano, IT
Abstract
10:30UB01.7A PRELIMINARY INTEGRATION FRAMEWORK PROVIDING CO-SIMULATION FOR ELECTRICAL SAFETY-CRITICAL SYSTEMS
Authors:
Hokeun Kim, Liangpeng Guo and Alberto Sangiovanni-Vincentelli, University of California, Berkeley, US
Abstract
10:30UB01.8A COMPLETE SUITE OF OPEN/FREE EDA TOOLS FOR PE PHYSICAL DESIGN
Authors:
Francesc Vila1, Jofre Pallarès1, Lluis Terés2, Jordi Carrabina3 and Keith Sabine4
1ICAS, IMB-CNM (CSIC), ES; 2ICAS, IMB-CNM (CSIC) and CAIAC, Universitat Autònoma de Barcelona, ES; 3CAIAC, Universitat Autònoma de Barcelona, ES; 4Peardrop design, ES
Abstract
12:30End of session
13:00Lunch Break in Auditorium Dauphine (Lunch and Learn Session) and Ecrins
Sandwich lunch in both locations (Lunch and Learn Session Sponsored by Mentor Graphics: "Grenoble Ecosystem to Provide Semiconductor Alternative Process for Advanced CMOS - 1300-1400 hrs; http://www.date-conference.com/conference/session/3.0)

2.1 Advanced Technology Nodes: Dependency on Collaboration

Date: Tuesday 19 March 2013
Time: 11:30 - 13:00
Location / Room: Oisans

Organiser:
Yervant Zorian, Synopsys, US

Chair:
Chris Edwards, EDA Tech, UK

Executives:
Douglas Pattullo, Director, TSMC Europe, NL
Naveed Sherwani, President, CoFounder & CEO, Open Silicon, US
Juan Rey, Senior Director, Mentor Graphics, US
Raj Yavatkar, Fellow, Intel, US

The continuous technology scaling and new multi-die solutions are dramatically impacting the business performance of semiconductor industry. This may also significantly affect the dependency between eco-system players necessitating stronger collaboration and interdependency between them. The executives in this session will discuss upcoming changes in the semiconductor industry and their impact on collaboration between the foundries, design service and IP providers, EDA companies, and the rest of the value chain.

TimeLabelPresentation Title
Authors
13:00End of session
Lunch Break in Auditorium Dauphine (Lunch and Learn Session) and Ecrins
Sandwich lunch in both locations (Lunch and Learn Session Sponsored by Mentor Graphics: "Grenoble Ecosystem to Provide Semiconductor Alternative Process for Advanced CMOS - 1300-1400 hrs; http://www.date-conference.com/conference/session/3.0)

2.2 Acceleration and Verification of ESL and Analog Systems

Date: Tuesday 19 March 2013
Time: 11:30 - 13:00
Location / Room: Belle-Etoile

Chair:
Alper Sen, Bogazici University, TR

Co-Chair:
Daniel Grosse, University of Bremen, DE

The session is centered around parallelization and verification of electronic designs during simulation. The first paper introduces an optimization technique for out-of-order parallel discrete event simulation of ESL designs using static analysis of potential hazards at compile time. The second paper describes a new way of parallelizing loosely-timed SystemC models using primitives that can explicitly capture durations for tasks. The third paper presents trade-offs estimation of fixed-point errors on linear time-invariant systems by combining advantages of statistical and analytical techniques. The final paper proposes a run-time algorithm to verify design properties of non-linear analogue circuits using efficient data structures.

TimeLabelPresentation Title
Authors
11:302.2.1(Best Paper Award Candidate)
OPTIMIZED OUT-OF-ORDER PARALLEL DISCRETE EVENT SIMULATION USING PREDICTIONS
Authors:
Weiwei Chen and Rainer Doemer, University of California, Irvine, US
Abstract
12:002.2.2PARALLEL PROGRAMMING WITH SYSTEMC FOR LOOSELY TIMED MODELS: A NON-INTRUSIVE APPROACH
Author:
Matthieu Moy, Grenoble University (Grenoble INP, Verimag), FR
Abstract
12:302.2.3ACCURACY VS SPEED TRADEOFFS IN THE ESTIMATION OF FIXED-POINT ERRORS ON LINEAR TIME-INVARIANT SYSTEMS
Authors:
David Novo1, Sara El Alaoui2 and Paolo Ienne1
1EPFL, CH; 2Al Akhawayn University, MA
Abstract
12:452.2.4RUNTIME VERIFICATION OF NONLINEAR ANALOG CIRCUITS USING INCREMENTAL TIME-AUGMENTED RRT ALGORITHM
Authors:
Seyed Nematollah Ahmadyan, Jayanand Asok Kumar and Shobha Vasudevan, University of Illinois at Urbana-Champaign, US
Abstract
13:00IP1-1, 933AN AUTOMATED PARALLEL SIMULATION FLOW FOR HETEROGENEOUS EMBEDDED SYSTEMS
Authors:
Seyed Hosein Attarzadeh Niaki and Ingo Sander, KTH Royal Institute of Technology, SE
Abstract
13:01IP1-2, 354MUTATION ANALYSIS WITH COVERAGE DISCOUNTING
Authors:
Peter Lisherness, Nicole Lesperance and Kwang-Ting Cheng, University of California, Santa Barbara, US
Abstract
13:02IP1-3, 772SCALABLE FAULT LOCALIZATION FOR SYSTEMC TLM DESIGNS
Authors:
Hoang M. Le, Daniel Große and Rolf Drechsler, University of Bremen, DE
Abstract
13:00End of session
Lunch Break in Auditorium Dauphine (Lunch and Learn Session) and Ecrins
Sandwich lunch in both locations (Lunch and Learn Session Sponsored by Mentor Graphics: "Grenoble Ecosystem to Provide Semiconductor Alternative Process for Advanced CMOS - 1300-1400 hrs; http://www.date-conference.com/conference/session/3.0)

2.3 Energy Optimization in Multi-core Systems

Date: Tuesday 19 March 2013
Time: 11:30 - 13:00
Location / Room: Stendahl

Chair:
Thidapat Chantem, Utah State University, US

Co-Chair:
William Fornaciari, Politecnico di Milano, IT

This session features papers addressing various issues arising in the design of multi-core systems, including process variability, real-time responsiveness, and dynamic user adaptation.

TimeLabelPresentation Title
Authors
11:302.3.1(Best Paper Award Candidate)
CHERRY-PICKING: EXPLOITING PROCESS VARIATIONS IN DARK-SILICON HOMOGENEOUS CHIP MULTI-PROCESSORS
Authors:
Yatish Turakhia1, Bharathwaj Raghunathan2, Siddharth Garg2 and Diana Marculescu3
1Indian Institute of Technology Bombay, IN; 2University of Waterloo, CA; 3Carnegie Mellon University, CA
Abstract
12:002.3.2ENERGY OPTIMIZATION WITH WORST-CASE DEADLINE GUARANTEE FOR PIPELINED MULTIPROCESSOR SYSTEMS
Authors:
Gang Chen1, Kai Huang1, Christian Buckl2 and Alios Knoll1
1Technische Universität München, DE; 2fortiss, DE
Abstract
12:302.3.3SELF-ADAPTIVE HYBRID DYNAMIC POWER MANAGEMENT FOR MANY-CORE SYSTEMS
Authors:
Muhammad Shafique, Benjamin Vogel and Jörg Henkel, Karlsruhe Institute of Technology, DE
Abstract
13:00IP1-4, 133SMARTCAP: USER EXPERIENCE-ORIENTED POWER ADAPTATION FOR SMARTPHONE'S APPLICATION PROCESSOR
Authors:
Xueliang Li, Guihai Yan, Yinhe Han and Xiaowei Li, Chinese Academy of Sciences, CN
Abstract
13:01IP1-5, 613RUNTIME POWER ESTIMATION OF MOBILE AMOLED DISPLAYS
Authors:
Dongwon Kim, Wonwoo Jung and Hojung Cha, Yonsei University, KR
Abstract
13:00End of session
Lunch Break in Auditorium Dauphine (Lunch and Learn Session) and Ecrins
Sandwich lunch in both locations (Lunch and Learn Session Sponsored by Mentor Graphics: "Grenoble Ecosystem to Provide Semiconductor Alternative Process for Advanced CMOS - 1300-1400 hrs; http://www.date-conference.com/conference/session/3.0)

2.4 Memory and Cache Architectures

Date: Tuesday 19 March 2013
Time: 11:30 - 13:00
Location / Room: Chartreuse

Chair:
Georgi Gaydadjiev, Chalmers University of Technology, SE

Co-Chair:
Todd Austin, Michigan University Ann Arbor, US

This session covers memory architectures to improve energy efficiency, reliability, performance, and access patterns in caches. The first paper proposes a mechanism to overcome sensitivity to access-time variations in L1 cache. The second paper introduces a new memory-addressing method and corresponding coherency protocol to handle two-dimensional memory access patterns. The third paper suggests a hybrid cache architecture composed of a hybrid SRAM and DRAM caches instead of two separate cache levels to reduce inter-core DRAM interferences. The last paper in the session uses a combination of SRAM and eDRAM to build energy-efficient L1 data caches that are resilient to errors when operating at near-threshold voltages.

TimeLabelPresentation Title
Authors
11:302.4.1(Best Paper Award Candidate)
AVICA: AN ACCESS-TIME VARIATION INSENSITIVE L1 CACHE ARCHITECTURE
Authors:
Seokin Hong and Soontea Kim, Korea Advanced Institute of Science and Technology, KR
Abstract
12:002.4.2DUAL-ADDRESSING MEMORY ARCHITECTURE FOR TWO-DIMENSIONAL MEMORY ACCESS PATTERNS
Authors:
Yen-Hao Chen and Yi-Yu Liu, Yuan Ze University, TW
Abstract
12:302.4.3ADAPTIVE CACHE MANAGEMENT FOR A COMBINED SRAM AND DRAM CACHE HIERARCHY FOR MULTI-CORES
Authors:
Fazal Hameed, Lars Bauer and Jörg Henkel, Karlsruhe Institute of Technology, DE
Abstract
12:452.4.4COMBINING RAM TECHNOLOGIES FOR HARD-ERROR RECOVERY IN L1 DATA CACHES WORKING AT VERY-LOW POWER MODES
Authors:
Vicente Lorente1, Alejandro Valero1, Julio Sahuquillo1, Salvador Petit1, Ramón Canal2, Pedro López1 and José Duato1
1Universitat Politècnica de València, ES; 2Universitat Politècnica de Catalunya, ES
Abstract
13:00IP1-6, 967A DUAL GRAIN HIT-MISS DETECTOR FOR LARGE DIE-STACKED DRAM CACHES
Authors:
Michel El Nacouzi, Islam Atta, Myrto Papadopoulou, Jason Zebchuk, Natalie Enright Jerger and Andreas Moshovos, University of Toronto, CA
Abstract
13:01IP1-7, 233REDUCING WRITES IN PHASE-CHANGE MEMORY ENVIRONMENTS BY USING EFFICIENT CACHE REPLACEMENT POLICIES
Authors:
Roberto Rodriguez, Fernando Castro, Daniel Chaver, Luis Pinuel and Francisco Tirado, Complutense University, ES
Abstract
13:00End of session
Lunch Break in Auditorium Dauphine (Lunch and Learn Session) and Ecrins
Sandwich lunch in both locations (Lunch and Learn Session Sponsored by Mentor Graphics: "Grenoble Ecosystem to Provide Semiconductor Alternative Process for Advanced CMOS - 1300-1400 hrs; http://www.date-conference.com/conference/session/3.0)

2.5 Communications, Multimedia, and Consumer Electronics

Date: Tuesday 19 March 2013
Time: 11:30 - 13:00
Location / Room: Meije

Chair:
Theocharis Theocharides, University of Cyprus, CY

Co-Chair:
Amer Baghdadi, Telecom Bretagne/Lab-STICC, FR

This session presents new architectures for digital communications as well as multi-media systems. The session consists of four papers. The first paper presents a low-complexity QR decomposition architecture, while the second paper presents a new methodology for managing SRAM memories for video applications. The third paper presents a parameterized flexible turbo decoder, and lastly, the fourth paper presents an H.264 intra-video encoder architecture.

TimeLabelPresentation Title
Authors
11:302.5.1LOW COMPLEXITY QR-DECOMPOSITION ARCHITECTURE USING THE LOGARITHMIC NUMBER SYSTEM
Authors:
Jochen Rust, Frank Ludwig and Steffen Paul, University of Bremen, DE
Abstract
12:002.5.2PERCEPTUAL QUALITY PRESERVING SRAM ARCHITECTURE FOR COLOR MOTION PICTURES
Authors:
Wen Yueh, Minki Cho and Saibal Mukhopadhyay, Georgia Institute of Technology, US
Abstract
12:302.5.3PARAMETERIZED AREA-EFFICIENT MULTI-STANDARD TURBO DECODER
Authors:
Purushotham Murugappa, Amer Baghdadi and Michel Jezequel, Telecom Bretagne, FR
Abstract
12:452.5.4AN H.264 QUAD-FULLHD LOW-LATENCY INTRA VIDEO ENCODER
Authors:
Muhammad Usman Karim Khan, Jan-Micha Borrmann, Lars Bauer, Muhammad Shafique and Jörg Henkel, Karlsruhe Institute of Technology, DE
Abstract
13:00IP1-8, 582A 100 GOPS ASP BASED BASEBAND PROCESSOR FOR WIRELESS COMMUNICATION
Authors:
Zhu Ziyuan, Tang Shan, Su Yongtao, Han Juan, Sun Gang and Shi Jinglin, Chinese Academy of Sciences, CN
Abstract
13:01IP1-9, 930HARDWARE-SOFTWARE COLLABORATIVE COMPLEXITY REDUCTION SCHEME FOR THE EMERGING HEVC INTRA ENCODER
Authors:
Muhammad Usman Karim Khan, Muhammad Shafique, Mateus Grellert da Silva and Jörg Henkel, Karlsruhe Institute of Technology, DE
Abstract
13:00End of session
Lunch Break in Auditorium Dauphine (Lunch and Learn Session) and Ecrins
Sandwich lunch in both locations (Lunch and Learn Session Sponsored by Mentor Graphics: "Grenoble Ecosystem to Provide Semiconductor Alternative Process for Advanced CMOS - 1300-1400 hrs; http://www.date-conference.com/conference/session/3.0)

2.6 HOT TOPIC: Reliability Challenges of Real-time Systems in Forthcoming Technology Nodes

Date: Tuesday 19 March 2013
Time: 11:30 - 13:00
Location / Room: Bayard

Organisers:
Dimitris Gizopoulos, University of Athens, GR
Said Hamdioui, Delft University of Technology, NL

Chair:
Said Hamdioui, Delft University of Technology, NL

Co-Chair:
Dimitris Gizopoulos, University of Athens, GR

Three leading researchers in various layers of system design and integration (technology, circuit, system, application) will present recent innovations in addressing emerging questions about reliability of the electronics of today's and tomorrow's real-time systems. Speakers will address the challenges from technology perspective, from circuit/IP perspective and from architectural and hardware/software integration perspective.

TimeLabelPresentation Title
Authors
11:302.6.1CHALLENGES IN ASSESSING AND ASSURING RELIABILITY OF NANO-SCALED CMOS TECHNOLOGIES
Author:
Guido Groeseneken, IMEC, BE
Abstract
12:002.6.2ADDA: ADAPTIVE DOUBLE-SAMPLING ARCHITECTURE FOR HIGHLY FLEXIBLE ROBUST DESIGN
Author:
Michael Nicolaidis, TIMA, FR
Abstract
12:302.6.3RELIABILITY CHALLENGES IN THE DESIGN OF CRITICAL EMBEDDED SYSTEMS
Authors:
Arnaud Grasset and Philippe Bonnot, Thales, FR
Abstract
13:00End of session
Lunch Break in Auditorium Dauphine (Lunch and Learn Session) and Ecrins
Sandwich lunch in both locations (Lunch and Learn Session Sponsored by Mentor Graphics: "Grenoble Ecosystem to Provide Semiconductor Alternative Process for Advanced CMOS - 1300-1400 hrs; http://www.date-conference.com/conference/session/3.0)

2.7 Safety Critical Real-Time Systems

Date: Tuesday 19 March 2013
Time: 11:30 - 13:00
Location / Room: Les Bans

Chair:
Giuseppe Lipari, ENS – Cachan, FR

Co-Chair:
Frank Slomka, University of Ulm, DE

This session presents novel methodologies for the design and analysis of safety critical real-time systems. The first paper concerns sensitivity analysis, which characterizes bounds on admissible system parameters. The contribution concerns the bounds on admissible activation pattern of the recurrent real-time tasks. The last two papers concern mixed-criticality scheduling, an effective approach to address diverse certification requirements of safety-critical systems that integrate multiple subsystems with different levels of criticality. The contribution of the first one includes schedulability analysis algorithms to enable integration of preemption threshold (technique which controls the degree of preemption) in order to reduce scheduler overhead and improve system predictability. The second one proposes an Early-Release EDF scheduling algorithm, which can judiciously manage the early release of low-criticality tasks without affecting the timeliness of high-criticality tasks.

TimeLabelPresentation Title
Authors
11:302.7.1SENSITIVITY ANALYSIS FOR ARBITRARY ACTIVATION PATTERNS IN REAL-TIME SYSTEMS
Authors:
Moritz Neukirchner, Sophie Quinton, Tobias Michaels, Philip Axer and Rolf Ernst, TU Braunschweig, DE
Abstract
12:002.7.2PT-AMC: INTEGRATING PREEMPTION THRESHOLDS INTO MIXED-CRITICALITY SCHEDULING
Authors:
Qingling Zhao1, Zonghua Gu1 and Haibo Zeng2
1Zhejiang University, CN; 2McGill University, CA
Abstract
12:302.7.3AN ELASTIC MIXED-CRITICALITY TASK MODEL AND ITS SCHEDULING ALGORITHM
Authors:
Hang Su and Dakai Zhu, The University of Texas at San Antonio, US
Abstract
13:00IP1-10, 152AN OPEN PLATFORM FOR MIXED-CRITICALITY REAL-TIME ETHERNET
Authors:
Gonzalo Carvajal1 and Sebastian Fischmeister2
1Universidad de Concepcion, CL; 2University of Waterloo, CA
Abstract
13:00End of session
Lunch Break in Auditorium Dauphine (Lunch and Learn Session) and Ecrins
Sandwich lunch in both locations (Lunch and Learn Session Sponsored by Mentor Graphics: "Grenoble Ecosystem to Provide Semiconductor Alternative Process for Advanced CMOS - 1300-1400 hrs; http://www.date-conference.com/conference/session/3.0)

2.8 HOT TOPIC: IP Subsystems: The next productivity wave?

Date: Tuesday 19 March 2013
Time: 11:30 - 13:00
Location / Room: Lesdigiueres (Exhibition Theatre)

Organisers:
Luciano Lavagno, Politecnico di Torino, IT
Wido Kruijtzer, Synopsys, NL

Chair:
Wido Kruijtzer, Synopsys, NL

Co-Chair:
Luciano Lavagno, Politecnico di Torino, IT

System-on-Chip (SoC) integrators have to deal with more and more complexity during integration of their architectures. For cost and time-to-market reasons, SoCs tend to be architected as a set of coarse-grain subsystems for recognized system functions like audio, video, connectivity, modem, etc. Such subsystem solutions consist of multiple integrated hardware IP blocks together with associated software. Till recently IP subsystems were mostly adopted internally within SoC integrators and were not yet available from traditional IP companies. However, in 2012 multiple companies announced the availably of IP subsystem solutions. This special session will provide an update on the state-of-the art with regards to IP subsystems and review if IP subsystems indeed will be the way forward to boost productivity of SoC design.

TimeLabelPresentation Title
Authors
11:302.8.1MODULAR SOC INTEGRATION WITH SUBSYSTEMS: THE AUDIO SUBSYSTEM CASE
Authors:
Pieter van der Wolf and Ruud Derwig, Synopsys, NL
Abstract
12:002.8.2CONFIGURABILITY IN IP SUBSYSTEMS: BASEBAND EXAMPLES
Authors:
Pierre-Xavier Thomas, Grant Martin, David Heine, Dennis Moolenaar and James Kim, Tensilica, US
Abstract
12:302.8.3CONFIGURABLE IO INTEGRATION TO REDUCE SYSTEM-ON-CHIP TIME TO MARKET: DDR, PCIE EXAMPLES
Authors:
Frank Martin and Peter Bennett, Cadence, UK
Abstract
12:452.8.4HIGH-PERFORMANCE IMAGING SUBSYSTEMS AND THEIR INTEGRATION IN MOBILE DEVICES
Authors:
Menno Lindwer1 and Mark Ruvald Pedersen2
1Intel, NL; 2Intel, DK
Abstract
13:00End of session
Lunch Break in Auditorium Dauphine (Lunch and Learn Session) and Ecrins
Sandwich lunch in both locations (Lunch and Learn Session Sponsored by Mentor Graphics: "Grenoble Ecosystem to Provide Semiconductor Alternative Process for Advanced CMOS - 1300-1400 hrs; http://www.date-conference.com/conference/session/3.0)

UB02 Session 2

Date: Tuesday 19 March 2013
Time: 12:30 - 14:30
Location / Room: Booth 46, Exhibition

TimeLabelPresentation Title
Authors
12:30UB02.1MICROTESK: ADVANCED TEST PROGRAM GENERATOR FOR MICROPROCESSORS
Authors:
Andrei Tatarnikov and Alexander Kamkin, Institute for System Programming of the Russian Academy of Sciences (ISP RAS), RU
Abstract
12:30UB02.2LIPS: AN IDE FOR SYSTEM DESIGN BASED ON NATURAL LANGUAGE PROCESSING
Authors:
Mathias Soeken, Oliver Keszöcze, Eugen Kuksa and Rolf Drechsler, University of Bremen, DE
Abstract
12:30UB02.3SYSTEMBUILDER: SYSTEM-LEVEL DESIGN PLATFORM FOR MULTICORE EMBEDDED SYSTEMS
Authors:
Yuki Ando, Yukihito Ishida, Shinya Honda and Hiroaki Takada, Nagoya University, JP
Abstract
12:30UB02.4FLEXIBLE AND HIGH-SPEED SYSTEM-LEVEL PERFORMANCE ANALYSIS USING HARDWARE-ACCELERATED SIMULATION
Authors:
Sascha Bischoff1, Andreas Sandberg2, Andreas Hansson3, Dam Sunwoo4, Ali G. Saidi4, Matthew Horsnell3 and Bashir M. Al-Hashimi1
1University of Southampton, UK; 2Uppsala University, SE; 3ARM, UK; 4ARM, US
Abstract
12:30UB02.5LOW-POWER SIGNAL PROCESSING PLATFORM BASED ON NON-UNIFORM SAMPLING AND EVENT-DRIVEN CIRCUITRY
Authors:
Laurent Fesquet1, Tugdual Le pelleter2, Taha Beyrouthy2, Yann Leroy2, Agnès Bonvilain2 and Robin Rolland-Girod3
1TIMA and CIME Nanotech, FR; 2TIMA, FR; 3CIME Nanotech, FR
Abstract
12:30UB02.6GENESIS: A GENETIC ALGORITHM BASED FPGA PLACER FOR MULTI-CORE PROCESSORS
Author:
Dionysios Diamantopoulos, ICCS - NTUA, GR
Abstract
12:30UB02.7EDA FOR SYSTEM LEVEL VERIFICATION: AN ADAPTIVE SYSTEM LEVEL VERIFICATION ENVIRONMENT
Authors:
Hassan Sohofi and Zainalabedin Navabi, University of Tehran, IR
Abstract
12:30UB02.8DAEDALUS^RT: A DESIGN FLOW FOR HARD-REAL-TIME EMBEDDED STREAMING SYSTEMS
Authors:
Mohamed Bamakhrama, Jiali Teddy Zhai, Sven van Haastregt and Todor Stefanov, Leiden University, NL
Abstract
12:30UB02.9EF3S: EVALUATION FRAMEWORK FOR FLASH-BASED SYSTEMS
Authors:
Marco Indaco, Salvatore Galfano, Stefano Di Carlo and Paolo Prinetto, Politecnico di Torino, IT
Abstract
14:30End of session
16:00Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

3.0 Special Lunch-Time Session: Grenoble ecosystem to provide semiconductor alternative process for advanced CMOS

Date: Tuesday 19 March 2013
Time: 13:00 - 14:00
Location / Room: Auditorium Dauphine

Organiser:
Bernard Courtois, CMP, FR

Chair:
Enrico Macii, Politecnico di Torino, IT

The session presents the Ultra-Thin Body and Box (UTBB) Fully Depleted SOI (FDSOI) process and shows that it meets requirements for high-performance at low-power and high energy efficiency: the 28nm FDSOI, 14nm FDSOI, and 10nm FDSOI nodes, offer a practical and cost-effective roadmap to shrink features and enable a significant boost for "green" products. With unmatched access resistance and electrostatic characteristics, planar SOI is superior to other technologies based on bulk CMOS technology or FinFET architecture. Product silicon demonstrates outstanding performances for low-power applications in consumer electronics, including tablets and mobile phones. The session will address manufacturing capabilities, design infrastructure and future R&D roadmaps.

TimeLabelPresentation Title
Authors
13:003.0.1FDSOI: FROM SUCCESSFUL COLLABORATIVE R&D TO SUCCESSFUL SILICON RESULTS
Author:
Philippe Magarshack, STMicroelectronics, FR
Abstract
13:203.0.2DESIGN INFRASTRUCTURE TO SUPPORT ADVANCED FDSOI BELOW 20NM
Author:
Jean-Marc Talbot, Mentor Graphics R&D center in Grenoble, FR
Abstract
13:403.0.3ROADMAP TOWARDS 10NM FDSOI NODE
Author:
Laurent Malier, CEA-Leti, FR
Abstract
14:00End of session
16:00Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

3.1 The Role of Prototyping in Today's SOCs

Date: Tuesday 19 March 2013
Time: 14:30 - 16:00
Location / Room: Oisans

Organiser:
Yervant Zorian, Synopsys, US

Chair:
Paul Dempsey, Editor-in-Chief, Tech Design Forum, The Curation Company, CN

Executives:
Ivo Bolsens, Senior Vice President & CTO, Xilinx, US
Joachim Kunkel, Senior Vice President & GM, Synopsys, US
Frank Schirrmeister, Senior Director, Cadence, US
Bipin Nair, General Manager, Infotech, DE

The widening gap between growing SOC complexity and designer productivity limits traditional system design methods and flows. This results in several new approaches and innovative methods that work to elevate the limitations of different aspects of complex SOC design, such as early investing in prototyping solutions. Executives in this session will discuss the role of prototyping and the new opportunities it may bring in designing today's complex chips.

TimeLabelPresentation Title
Authors
16:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

3.2 PANEL: The Heritage of Mead & Conway: What Has Remained the Same, What Was Missed, What Has Changed, What Lies Ahead

Date: Tuesday 19 March 2013
Time: 14:30 - 16:00
Location / Room: Belle-Etoile

Organiser:
Marco Casale-Rossi, Synopsys, US

Chair:
Alberto Sangiovanni-Vincentelli, UCB, US

About 30 years ago, Electronics Magazine awarded two electrical engineers and computer scientists, Carver Mead and Lynn Conway for their contribution to VLSI chips design; in 1982, the so called Mead & Conway methods, taught at 100+ universities all over the world, "not only have helped spawn a common design culture so necessary in the VLSI era, but have greatly increased interaction between university and industry so as to stimulate research by both"; concepts such as separation of design from manufacturing, design rules, silicon foundries, addressing complexity through design methodology, new, electronic representations of design data, have enabled tens of thousands of chip designers, and tens of thousands of chip designs. Today, as Moore's Law - a term coined by Carver Mead - has brought as from 10 microns to 10 nanometers, what is the heritage of Mead & Conway? UCB Professor Alberto Sangiovanni-Vincentelli will moderate an industry and research panel, to discuss what has remained the same, what was missed, what has changed, and what lies ahead.

Panelists:

  • Luca Carloni, Columbia University, US
  • Bernard Courtois, CMP, FR
  • Hugo De Man, K.U. Leuven & IMEC, BE
  • Antun Domic, Synopsys, US
  • Jan Rabaey, University of California, Berkeley, US
16:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

3.3 Addressing Process and Delay Variation in High-Level Synthesis

Date: Tuesday 19 March 2013
Time: 14:30 - 16:00
Location / Room: Stendahl

Chair:
Lars Bauer, Karlsruhe Institute of Technology, DE

Co-Chair:
Giovanni Ansaloni, EPFL, CH

The first two papers target the problem of process variation and aging issues for high-level and instruction-set synthesis. The last paper incorporates delay variations arising from speculative adder structures in high-level synthesis.

TimeLabelPresentation Title
Authors
14:303.3.1(Best Paper Award Candidate)
PROFIT MAXIMIZATION THROUGH PROCESS VARIATION AWARE HIGH LEVEL SYNTHESIS WITH SPEED BINNING
Authors:
Zhao Mengying1, Alex Orailoglu2 and Xue Chun Jason1
1City University of Hong Kong, HK; 2University of California, US
Abstract
15:003.3.2INSTRUCTION-SET EXTENSION UNDER PROCESS VARIATION AND AGING EFFECTS
Authors:
Yuko Hara-Azumi1, Farshad Firouzi2, Saman Kiamehr2 and Mehdi Tahoori2
1Nara Institute of Science and Technology, JP; 2Karlsruhe Institute of Technology, DE
Abstract
15:303.3.3MULTISPECULATIVE ADDITIVE TREES IN HIGH-LEVEL SYNTHESIS
Authors:
Alberto A. Del Barrio1, Román Hermida1, Seda O. Memik2, José M. Mendías1 and María C. Molina1
1Complutense University of Madrid, ES; 2Northwestern University, US
Abstract
16:00IP1-11, 528MULTI-PUMPING FOR RESOURCE REDUCTION IN FPGA HIGH-LEVEL SYNTHESIS
Authors:
Andrew Canis, Jason Anderson and Stephen Brown, University of Toronto, CA
Abstract
16:01IP1-12, 380RESOURCE-CONSTRAINED HIGH-LEVEL DATAPATH OPTIMIZATION IN ASIP DESIGN
Authors:
Yuankai Chen and Hai Zhou, Northwestern University, US
Abstract
16:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

3.4 Microarchitectural Techniques for Reliability

Date: Tuesday 19 March 2013
Time: 14:30 - 16:00
Location / Room: Chartreuse

Chair:
Todd Austin, Michigan University Ann Arbor, US

Co-Chair:
Mladen Berekovic, Technical University of Braunschweig, DE

This session introduces a variety of papers regarding reliability issues, which are managed by fault tolerance, fault avoidance, and error correction techniques. The first paper proposes to aggressively utilize computation results from error-prone processors. The second one tries to avoid voltage drops in multi-core processors by focusing on the inter-core power interactions. The third and fourth papers propose error detection and correction techniques; the former one is for memories and the latter one for logic circuits.

TimeLabelPresentation Title
Authors
14:303.4.1EXTRACTING USEFUL COMPUTATION FROM ERROR-PRONE PROCESSORS FOR STREAMING APPLICATIONS
Authors:
Yavuz Yetim, Margaret Martonosi and Sharad Malik, Princeton University, US
Abstract
15:003.4.2ORCHESTRATOR: A LOW-COST SOLUTION TO REDUCE VOLTAGE EMERGENCIES FOR MULTI-THREADED APPLICATIONS
Authors:
Xing Hu, Guihai Yan, Yu Hu and Xiaowei Li, Chinese Academy of Sciences, CN
Abstract
15:303.4.3MEMORY ARRAY PROTECTION: CHECK ON READ OR CHECK ON WRITE?
Authors:
Panagiota Nikolaou1, Yanos Sazeides1, Lorena Ndreou1, Emre Ozer2 and Sachin Idgunji3
1University of Cyprus, CY; 2ARM, UK; 3ARM, US
Abstract
15:453.4.4FAULTM: ERROR DETECTION AND RECOVERY USING HARDWARE TRANSACTIONAL MEMORY
Authors:
Gulay Yalcin, Osman Unsal and Adrian Cristal, Barcelona Supercomputing Center, ES
Abstract
16:00IP1-13, 674PHOENIX: REVIVING MLC BLOCKS AS SLC TO EXTEND NAND FLASH DEVICES LIFETIME
Authors:
Xavier Jimenez, David Novo and Paolo Ienne, École Polytechnique Fédérale de Lausanne, CH
Abstract
16:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

3.5 Energy Efficient Mobile and Cloud Computing Systems

Date: Tuesday 19 March 2013
Time: 14:30 - 16:00
Location / Room: Meije

Chair:
Ayse K. Coskun, Boston University, US

Co-Chair:
Theocharis Theocharides, University of Cyprus, CY

The session focuses on modelling, model-driven optimization, and low-energy architectures for energy-efficient computing in mobile devices and cloud computing systems. The first paper explores new computationally inexpensive detection methods of thermal behavior on multi-core architectures. The second paper presents a novel way of computing by using energy-efficient 3D wide memory interfaces. Finally, the third paper presents a low-power FFT implementation for multiple applications.

TimeLabelPresentation Title
Authors
14:303.5.1(Best Paper Award Candidate)
SCC THERMAL MODEL IDENTIFICATION VIA ADVANCED BIAS-COMPENSATED LEAST-SQUARES
Authors:
Roberto Diversi, Andrea Bartolini, Andrea Tilli, Francesco Beneventi and Luca Benini, University of Bologna, IT
Abstract
15:003.5.2SYSTEM AND CIRCUIT LEVEL POWER MODELING OF ENERGY-EFFICIENT 3D-STACKED WIDE I/O DRAMS
Authors:
Karthik Chandrasekar1, Christian Weis2, Benny Akesson3, Norbert Wehn2 and Kees Goossens4
1Delft University of Technology, NL; 2University of Kaiserslautern, DE; 3Polytechnic Institute of Porto, PT; 4Eindhoven University of Technology, NL
Abstract
15:153.5.3DESIGN OF LOW POWER, HIGH PERFORMANCE SYNCHRONOUS AND ASYNCHRONOUS 64-POINT FFT
Authors:
William Lee1, Vikas Vij1, Kenneth Stevens1 and Anthony Thatcher2
1University of Utah, US; 2, US
Abstract
15:303.5.4(Best Paper Award Candidate)
A MULTI-LEVEL MONTE CARLO FPGA ACCELERATOR FOR OPTION PRICING IN THE HESTON MODEL
Authors:
Christian de Schryver, Pedro Torruella and Norbert Wehn, University of Kaiserslautern, DE
Abstract
16:00IP1-14, 88NON-SPECULATIVE DOUBLE-SAMPLING TECHNIQUE TO INCREASE ENERGY-EFFICIENCY IN A HIGH-PERFORMANCE PROCESSOR
Authors:
Junyoung Park, Ameya Chaudhari and Jacob Abraham, The University of Texas at Austin, US
Abstract
16:01IP1-15, 510USER-AWARE ENERGY EFFICIENT STREAMING STRATEGY FOR SMARTPHONE BASED VIDEO PLAYBACK APPLICATIONS
Authors:
Hao Shen and Qinru Qiu, Syracuse University, US
Abstract
16:02IP1-16, 379UTILITY-AWARE DEFERRED LOAD BALANCING IN THE CLOUD DRIVEN BY DYNAMIC PRICING OF ELECTRICITY
Authors:
Muhammad Adnan and Rajesh Gupta, University of California, San Diego, US
Abstract
16:03IP1-17, 810LEAKAGE AND TEMPERATURE AWARE SERVER CONTROL FOR IMPROVING ENERGY EFFICIENCY IN DATA CENTERS
Authors:
Marina Zapater1, José L. Ayala2, José M. Moya3, Kalyan Vaidyanathan4, Kenny Gross4 and Ayse K. Coskun5
1CEI Campus Moncloa UCM-UPM, ES; 2Universidad Complutense de Madrid, ES; 3Universidad Politécnica de Madrid, ES; 4University of California, San Diego, US; 5Boston University, US
Abstract
16:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

3.6 Dealing with Timing Variation in Advanced Technologies

Date: Tuesday 19 March 2013
Time: 14:30 - 16:00
Location / Room: Bayard

Chair:
Bram Kruseman, NXP, NL

Co-Chair:
Saqib Khursheed, University of Southampton, UK

To get the best performance one needs to minimize slack, however, this is getting challenging since one needs to take into account many aspects. The papers in this session present the benefits of taking aging into account during the design phase, how to measure in-situ the slack, and test pattern generation that takes into account statistical variation to improve coverage.

TimeLabelPresentation Title
Authors
14:303.6.1(Best Paper Award Candidate)
MTTF-BALANCED PIPELINE DESIGN
Authors:
Fabian Oboril and Mehdi Tahoori, Karlsruhe Institute of Technology, DE
Abstract
15:003.6.2EFFICIENT VARIATION-AWARE STATISTICAL DYNAMIC TIMING ANALYSIS FOR DELAY TEST APPLICATIONS
Authors:
Marcus Wagner and Hans-Joachim Wunderlich, University of Stuttgart, DE
Abstract
15:303.6.3SLACKPROBE: A LOW OVERHEAD IN SITU ON-LINE TIMING SLACK MONITORING METHODOLOGY
Authors:
Liangzhen Lai1, Vikas Chandra2, Rob Aitken2 and Puneet Gupta1
1University of California, Los Angeles, US; 2ARM, US
Abstract
16:00IP1-18, 224CAPTURING POST-SILICON VARIATIONS BY LAYOUT-AWARE PATH-DELAY TESTING
Authors:
Xiaolin Zhang, Jing Ye, Yu Hu and Xiaowei Li, Chinese Academy of Sciences, CN
Abstract
16:01IP1-19, 678ADAPTIVE REDUCTION OF THE FREQUENCY SEARCH SPACE FOR MULTI-VDD DIGITAL CIRCUITS
Authors:
Chandra Suresh1, Ender Yilmaz2, Ozgur Sinanoglu1 and Sule Ozev3
1NYU Abu Dhabi, AE; 2Freescale, US; 3Arizona State University, US
Abstract
16:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

3.7 Timing Analysis

Date: Tuesday 19 March 2013
Time: 14:30 - 16:00
Location / Room: Les Bans

Chair:
Giuseppe Lipari, ENS – Cachan, FR

Co-Chair:
Benny Åkesson, TU Eindhoven, NL

The session focuses on low-level timing analysis of real-time systems. The first paper presents a novel way of analysing the behaviour of FIFO caches, which is known to be a demanding challenge. The second paper introduces the timing analysis of multi-core processors in an automotive setting, when this is subject to mode changes. The last paper explores the analysis of contention on shared SDRAM memory under a credit-controlled static priority arbitration scheme.

TimeLabelPresentation Title
Authors
14:303.7.1(Best Paper Award Candidate)
FIFO CACHE ANALYSIS FOR WCET ESTIMATION: A QUANTITATIVE APPROACH
Authors:
Nan Guan1, Xinping Yang1, Mingsong Lv2 and Wang Yi1
1Uppsala University, SE; 2Northeastern University, CN
Abstract
15:003.7.2TIMING ANALYSIS OF MULTI-MODE APPLICATIONS ON AUTOSAR CONFORM MULTI-CORE SYSTEMS
Authors:
Mircea Negrean, Sebastian Klawitter and Rolf Ernst, TU Braunschweig, DE
Abstract
15:303.7.3BOUNDING SDRAM INTERFERENCE: DETAILED ANALYSIS VS. LATENCY-RATE ANALYSIS
Authors:
Hardik Shah1, Alois Knoll2 and Benny Akesson3
1fortiss, DE; 2Technische Universität München, DE; 3Polytechnic Institute of Porto, PT
Abstract
16:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

3.8 HOT TOPIC: Design for Variability, Manufacturability, Reliability, and Debug: Many Faces of the Same Coin?

Date: Tuesday 19 March 2013
Time: 14:30 - 16:00
Location / Room: Lesdigiueres (Exhibition Theatre)

Organiser:
Vikas Chandra, ARM, US

Chair:
Vikas Chandra, ARM, US

Co-Chair:
Kartik Mohanram, University of Pittsburgh, US

Complex SoCs of the future are subject to various sources of variability, reliability failures and design errors (logical or electrical) due to sheer design complexity, and marginal behaviors induced by uncertainties in manufacturing processes, temporal variability and operating conditions. In this session, we will cover this entire spectrum ranging from state-of-the-art techniques for manufacturability, variability and aging mitigation to effective post-silicon debug methods and everything in between

TimeLabelPresentation Title
Authors
14:303.8.1ROLE OF DESIGN IN MULTIPLE PATTERNING: TECHNOLOGY DEVELOPMENT, DESIGN ENABLEMENT AND PROCESS CONTROL
Authors:
Rani A. Ghaida1 and Puneet Gupta2
1GlobalFoundries, US; 2University of California, Los Angeles, US
Abstract
15:003.8.2OVERCOMING POST-SILICON VALIDATION CHALLENGES THROUGH QUICK ERROR DETECTION (QED)
Authors:
David Lin1, Ted Hong1, Yanjing Li1, Farzan Fallah1, Donald S. Gardner2, Nagib Hakim2 and Subhasish Mitra1
1Stanford University, US; 2Intel, US
Abstract
15:303.8.3STOCHASTIC DEGRADATION MODELING AND SIMULATION FOR ANALOG INTEGRATED CIRCUITS IN NANOMETER CMOS
Authors:
Georges Gielen and Elie Maricau, KU Leuven, BE
Abstract
16:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

UB03 Session 3

Date: Tuesday 19 March 2013
Time: 14:30 - 16:30
Location / Room: Booth 46, Exhibition

TimeLabelPresentation Title
Authors
14:30UB03.1NOC SYSTEM GENERATOR: NOC SYSTEM GENERATOR - A TOOL FOR FAST PROTOTYPING OF MULTI-CORE SYSTEMS ON FPGAS
Authors:
Johnny Öberg, Francesco Robino, Hosein Attarzadeh and Ingo Sander, KTH Royal Institute of Technology, SE
Abstract
14:30UB03.2SYNTHORUS-2: AUTOMATIC PROTOTYPING ON FPGA FROM PSL
Authors:
Fatemeh Javaheri, Katell Morin‐Allory, Alexandre Porcher and Dominique Borrione, TIMA Lab, FR
Abstract
14:30UB03.3NAGA HIGH-PERFORMANCE ARRAY PROCESSOR: ARCHITECTURAL SIMULATION AND APPLICATION ANALYSIS
Authors:
Sumeet S. Kumar and Rene van Leuken, Delft University of Technology, NL
Abstract
14:30UB03.4STBA: A NOVEL ANALYTICAL METHOD FOR WORST CASE RESPONSE TIME ESTIMATION OF DISTRIBUTED EMBEDDED SYSTEMS
Authors:
Junchul Choi1, Jinwoo Kim1, Hyojin Ha1, Hyunok Oh2 and Soonhoi Ha1
1Seoul National University, KR; 2Hanyang University, KR
Abstract
14:30UB03.5FPGA-BASED IP-CORES LIBRARY FOR ADVANCED IMAGE PROCESSING IN SPACE APPLICATIONS
Authors:
Pascal Trotta, Paolo Prinetto and Daniele Rolfo, Politecnico di Torino, IT
Abstract
14:30UB03.6ZAMIACAD: VHDL DESIGN DEBUG FRAMEWORK BASED ON ZAMIACAD
Authors:
Maksim Jenihhin, Valentin Tihhomirov, Anton Chepurov, Saif Abrar Syed and Jaan Raik, Tallinn University of Technology, EE
Abstract
14:30UB03.7ID.FIX: A SOFTWARE INFRASTRUCTURE FOR THE DESIGN OF EMBEDDED SYSTEMS USING FIXED-POINT ARITHMETIC
Authors:
Olivier Sentieys1, Daniel Ménard2 and Romuald Rocher3
1INRIA, FR; 2INSA Rennes, FR; 3University of Rennes 1, FR
Abstract
14:30UB03.8ASAM TOOLS DEMONSTRATION
Authors:
Felipe Chies1, Rosilde Corvino2, Erkan Diken2, Christof Douma3, Agostino Galluzzo4, Deepak Gangadharan5, Roel Jordans2, Lech Jozwiak2, Bart Kienhuis6, Menno Lindwer1, Jan Madsen5, Paolo Meloni7, Laura Micconi5, Giuseppe Notarangelo4, Sebastiano Pomata7, Luigi Raffo7 and Giuseppe Tuveri7
1Intel, NL; 2Eindhoven University of Technology, NL; 3ACE, NL; 4ST, IT; 5DTU, DK; 6Compaan, NL; 7UNICA, IT
Abstract
14:30UB03.9SYNTHESIZING ABSTRACT COMMUNICATIONS TO RTL STANDARD BUS STRUCTURES
Authors:
Somayeh Sadeghi-Kohan, Rasoul Jafari, Ghazaleh Vazhbakht, Parastoo Kamranfar, Reza Namazian, Mahya Saffarpour and Zain Navabi, University of Tehran, IR
Abstract
16:30End of session
18:30Evening Reception offered by the City of Grenoble in Several serving points inside the Exhibition Hall

IP1 Interactive Presentations

Date: Tuesday 19 March 2013
Time: 16:00 - 16:30
Location / Room: Exhibition Hall (espace accueil)

Interactive Presentations run simulatenously during a 30-minute slot. A poster associated to the IP paper is on display throughout the afternoon. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session, prior to the actual Interactive Presentation.

LabelPresentation Title
Authors
IP1-1AN AUTOMATED PARALLEL SIMULATION FLOW FOR HETEROGENEOUS EMBEDDED SYSTEMS
Authors:
Seyed Hosein Attarzadeh Niaki and Ingo Sander, KTH Royal Institute of Technology, SE
Abstract
IP1-2MUTATION ANALYSIS WITH COVERAGE DISCOUNTING
Authors:
Peter Lisherness, Nicole Lesperance and Kwang-Ting Cheng, University of California, Santa Barbara, US
Abstract
IP1-3SCALABLE FAULT LOCALIZATION FOR SYSTEMC TLM DESIGNS
Authors:
Hoang M. Le, Daniel Große and Rolf Drechsler, University of Bremen, DE
Abstract
IP1-4SMARTCAP: USER EXPERIENCE-ORIENTED POWER ADAPTATION FOR SMARTPHONE'S APPLICATION PROCESSOR
Authors:
Xueliang Li, Guihai Yan, Yinhe Han and Xiaowei Li, Chinese Academy of Sciences, CN
Abstract
IP1-5RUNTIME POWER ESTIMATION OF MOBILE AMOLED DISPLAYS
Authors:
Dongwon Kim, Wonwoo Jung and Hojung Cha, Yonsei University, KR
Abstract
IP1-6A DUAL GRAIN HIT-MISS DETECTOR FOR LARGE DIE-STACKED DRAM CACHES
Authors:
Michel El Nacouzi, Islam Atta, Myrto Papadopoulou, Jason Zebchuk, Natalie Enright Jerger and Andreas Moshovos, University of Toronto, CA
Abstract
IP1-7REDUCING WRITES IN PHASE-CHANGE MEMORY ENVIRONMENTS BY USING EFFICIENT CACHE REPLACEMENT POLICIES
Authors:
Roberto Rodriguez, Fernando Castro, Daniel Chaver, Luis Pinuel and Francisco Tirado, Complutense University, ES
Abstract
IP1-8A 100 GOPS ASP BASED BASEBAND PROCESSOR FOR WIRELESS COMMUNICATION
Authors:
Zhu Ziyuan, Tang Shan, Su Yongtao, Han Juan, Sun Gang and Shi Jinglin, Chinese Academy of Sciences, CN
Abstract
IP1-9HARDWARE-SOFTWARE COLLABORATIVE COMPLEXITY REDUCTION SCHEME FOR THE EMERGING HEVC INTRA ENCODER
Authors:
Muhammad Usman Karim Khan, Muhammad Shafique, Mateus Grellert da Silva and Jörg Henkel, Karlsruhe Institute of Technology, DE
Abstract
IP1-10AN OPEN PLATFORM FOR MIXED-CRITICALITY REAL-TIME ETHERNET
Authors:
Gonzalo Carvajal1 and Sebastian Fischmeister2
1Universidad de Concepcion, CL; 2University of Waterloo, CA
Abstract
IP1-11MULTI-PUMPING FOR RESOURCE REDUCTION IN FPGA HIGH-LEVEL SYNTHESIS
Authors:
Andrew Canis, Jason Anderson and Stephen Brown, University of Toronto, CA
Abstract
IP1-12RESOURCE-CONSTRAINED HIGH-LEVEL DATAPATH OPTIMIZATION IN ASIP DESIGN
Authors:
Yuankai Chen and Hai Zhou, Northwestern University, US
Abstract
IP1-13PHOENIX: REVIVING MLC BLOCKS AS SLC TO EXTEND NAND FLASH DEVICES LIFETIME
Authors:
Xavier Jimenez, David Novo and Paolo Ienne, École Polytechnique Fédérale de Lausanne, CH
Abstract
IP1-14NON-SPECULATIVE DOUBLE-SAMPLING TECHNIQUE TO INCREASE ENERGY-EFFICIENCY IN A HIGH-PERFORMANCE PROCESSOR
Authors:
Junyoung Park, Ameya Chaudhari and Jacob Abraham, The University of Texas at Austin, US
Abstract
IP1-15USER-AWARE ENERGY EFFICIENT STREAMING STRATEGY FOR SMARTPHONE BASED VIDEO PLAYBACK APPLICATIONS
Authors:
Hao Shen and Qinru Qiu, Syracuse University, US
Abstract
IP1-16UTILITY-AWARE DEFERRED LOAD BALANCING IN THE CLOUD DRIVEN BY DYNAMIC PRICING OF ELECTRICITY
Authors:
Muhammad Adnan and Rajesh Gupta, University of California, San Diego, US
Abstract
IP1-17LEAKAGE AND TEMPERATURE AWARE SERVER CONTROL FOR IMPROVING ENERGY EFFICIENCY IN DATA CENTERS
Authors:
Marina Zapater1, José L. Ayala2, José M. Moya3, Kalyan Vaidyanathan4, Kenny Gross4 and Ayse K. Coskun5
1CEI Campus Moncloa UCM-UPM, ES; 2Universidad Complutense de Madrid, ES; 3Universidad Politécnica de Madrid, ES; 4University of California, San Diego, US; 5Boston University, US
Abstract
IP1-18CAPTURING POST-SILICON VARIATIONS BY LAYOUT-AWARE PATH-DELAY TESTING
Authors:
Xiaolin Zhang, Jing Ye, Yu Hu and Xiaowei Li, Chinese Academy of Sciences, CN
Abstract
IP1-19ADAPTIVE REDUCTION OF THE FREQUENCY SEARCH SPACE FOR MULTI-VDD DIGITAL CIRCUITS
Authors:
Chandra Suresh1, Ender Yilmaz2, Ozgur Sinanoglu1 and Sule Ozev3
1NYU Abu Dhabi, AE; 2Freescale, US; 3Arizona State University, US
Abstract

UB04 Session 4

Date: Tuesday 19 March 2013
Time: 16:30 - 18:30
Location / Room: Booth 46, Exhibition

TimeLabelPresentation Title
Authors
16:30UB04.1SYSTEMBUILDER: SYSTEM-LEVEL DESIGN PLATFORM FOR MULTICORE EMBEDDED SYSTEMS
Authors:
Yuki Ando, Yukihito Ishida, Shinya Honda and Hiroaki Takada, Nagoya University, JP
Abstract
16:30UB04.2EDKDSP: REPROGRAMMABLE FLOATING POINT ACCELERATORS ON KINTEX FPGA WITH HDMI
Author:
Jiri Kadlec, UTIA AV CR v.v.i., CZ
Abstract
16:30UB04.3FPGA-BASED IN SYSTEM MULTIPLE LRU CACHE SIMULATION
Authors:
Josef Schneider, Jorgen Peddersen and Sridevan Parameswaran, University of New South Wales, AU
Abstract
16:30UB04.4ASAP: AN OPEN-SOURCE FRAMEWORK FOR EARLY VALIDATION OF HETEROGENEOUS RECONFIGURABLE SYSTEMS
Authors:
Christian Pilato, Alessandro Antonio Nacci, Gianluca Durelli, Riccardo Cattaneo, Marco Domenico Santambrogio and Donatella Sciuto, Politecnico di Milano, IT
Abstract
16:30UB04.5FPGA-BASED IP-CORES LIBRARY FOR ADVANCED IMAGE PROCESSING IN SPACE APPLICATIONS
Authors:
Pascal Trotta, Paolo Prinetto and Daniele Rolfo, Politecnico di Torino, IT
Abstract
16:30UB04.6ZAMIACAD: VHDL DESIGN DEBUG FRAMEWORK BASED ON ZAMIACAD
Authors:
Maksim Jenihhin, Valentin Tihhomirov, Anton Chepurov, Saif Abrar Syed and Jaan Raik, Tallinn University of Technology, EE
Abstract
16:30UB04.7A COMPLETE SUITE OF OPEN/FREE EDA TOOLS FOR PE PHYSICAL DESIGN
Authors:
Francesc Vila1, Jofre Pallarès1, Lluis Terés2, Jordi Carrabina3 and Keith Sabine4
1ICAS, IMB-CNM (CSIC), ES; 2ICAS, IMB-CNM (CSIC) and CAIAC, Universitat Autònoma de Barcelona, ES; 3CAIAC, Universitat Autònoma de Barcelona, ES; 4Peardrop design, ES
Abstract
16:30UB04.8HIERARCHICAL ESL FAULT SIMULATION PACKAGE
Authors:
Somayeh Sadeghi-Kohan1, Arash Akhoundi1, Farnaz Forooghifar1, Elmira Karimi2, Mohammad Ghasemi1, Zahra Najafi1, Saba Amanollahi3 and Zain Navabi1
1University of Tehran, IR; 2Sharif University, IR; 3Shahid Beheshti University, IR
Abstract
18:30End of session
Evening Reception offered by the City of Grenoble in Several serving points inside the Exhibition Hall

4.1 Is reusing off-the-shelf Semiconductor IP possible today?

Date: Tuesday 19 March 2013
Time: 17:00 - 18:30
Location / Room: Oisans

Organiser:
Yervant Zorian, Synopsys, US

Chair:
Louise Joselyn, New Electronics, UK

Executives:
Grant Martin, CTO, Tensilica, US
Joachim Kunkel, Senior Vice President & GM, Synopsys, US
John Goodacre, Director, CPU Group, ARM, UK

While today's SOCs systematically use a range of IP blocks, meeting end product requirements, such as power, performance and area, remain an obstacle on reusing off-the-shelf IP blocks. The speakers in this executive session will address the current trends and challenges in the semiconductor IP industry and discuss the level of customization versus reuse needed to meet today's SOC requirements.

TimeLabelPresentation Title
Authors
18:30End of session
Evening Reception offered by the City of Grenoble in Several serving points inside the Exhibition Hall

4.2 The Quest for Better NoCs

Date: Tuesday 19 March 2013
Time: 17:00 - 18:30
Location / Room: Belle-Etoile

Chair:
Pascal Vivet, CEA-LETI, FR

Co-Chair:
Benny Åkesson, University of Technology Eindhoven, NL

This session focuses on the architectural side of NoC design, starting with an asynchronous switch architecture and related tool flow for implementation. The next paper proposes an efficient, single-cycle-propagation technique that reduces NoC traversal latencies. The last paper analyzes the trade-offs of port sharing in NoC routers.

TimeLabelPresentation Title
Authors
17:004.2.1(Best Paper Award Candidate)
A TRANSITION-SIGNALING BUNDLED DATA NOC SWITCH ARCHITECTURE FOR COST-EFFECTIVE GALS MULTICORE SYSTEMS
Authors:
Alberto Ghiribaldi1, Davide Bertozzi1 and Steven M. Nowick2
1University of Ferrara, IT; 2Columbia University, US
Abstract
17:304.2.2SMART: A SINGLE-CYCLE RECONFIGURABLE NOC FOR SOC APPLICATIONS
Authors:
Chia-Hsin Owen Chen, Sunghyun Park, Tushar Krishna, Suvinay Subramanian, Li-Shiuan Peh and Anantha P. Chandrakasan, Massachusetts Institute of Technology, US
Abstract
18:004.2.3SWITCH FOLDING: NETWORK-ON-CHIP ROUTERS WITH TIME-MULTIPLEXED OUTPUT PORTS
Authors:
Giorgos Dimitrakopoulos1, Nikodimos Georgiadis2, Chrysostomos Nicopoulos2 and Emmanouil Kalligeros3
1Democritus University of Thrace, GR; 2University of Cyprus, CY; 3University of the Aegean, GR
Abstract
18:30IP2-1, 615AN EFFICIENT NETWORK ON-CHIP ARCHITECTURE BASED ON ISOLATING LOCAL AND NON-LOCAL COMMUNICATIONS
Authors:
Vahideh Akhlaghi1, Mehdi Kamal1, Ali Afzali-Kusha1 and Massoud Pedram2
1University of Tehran, IR; 2University of Southern California, US
Abstract
18:31IP2-2, 588SVR-NOC: A PERFORMANCE ANALYSIS TOOL FOR NETWORK-ON-CHIPS USING LEARNING-BASED SUPPORT VECTOR REGRESSION MODEL
Authors:
Zhiliang Qian1, Da-Cheng Juan2, Paul Bogdan2, Chi-Ying Tsui1, Diana Marculescu2 and Radu Marculescu2
1Hong Kong University of Science and Technology, HK; 2Carnegie Mellon University, US
Abstract
18:30End of session
Evening Reception offered by the City of Grenoble in Several serving points inside the Exhibition Hall

4.3 EMBEDDED TUTORIAL: Reliability Analysis Reloaded: How Will We Survive?

Date: Tuesday 19 March 2013
Time: 17:00 - 18:30
Location / Room: Stendahl

Organisers:
Matteo Sonza Reorda, Politecnico di Torino, IT
Goerschwin Fey, University of Bremen, DE

Chair:
Bernd Becker, University of Freiburg, DE

Co-Chair:
Xavier Vera, Intel, ES

Concepts for reliability analysis have been a hot topic in research and industry ever since the introduction of electronic systems over 40 years ago. Reliability problems are expected to increase rapidly for future technology nodes, for many reasons. The sheer complexity of today's and future "more Moore" and "more than Moore" systems as well as the huge universe of potential faults requires reliability analysis to be revisited from this new perspective. This embedded tutorial will focus on reliability analysis from both an academic and an industrial perspective, including different layers of abstraction. The first talk will concentrate on the lowest layer from an industrial perspective, i.e. how we can find models for device-level reliability that may be used for determining the reliability of a system. The second talk will approach state-of-the-art techniques from an academic point of view to evaluate the reliability of complex systems, including virtualization environments. The tutorial will be completed with a talk that describes the development of safety critical systems in industrial automation, in particular pointing out how reliability evaluation is handled on the basis of current safety standards.

TimeLabelPresentation Title
Authors
17:004.3.1RELIABILITY EVALUATION AT THE DEVICE LEVEL AND ITS IMPACT ON DESIGN
Author:
Rob Aitken, ARM, US
Abstract
17:304.3.2RELIABILITY EVALUATION AT THE SYSTEM LEVEL
Author:
Z. T. Kalbarczyk, University of Illinois at Urbana-Champaign, AE
Abstract
18:004.3.3ON EVALUATING THE RELIABILITY OF INDUSTRIAL PRODUCTS AND THE IMPACT OF SAFETY STANDARDS IN AUTOMATION INDUSTRY
Author:
Frank Reichenbach, ABB Corporate Research, NO
Abstract
18:30End of session
Evening Reception offered by the City of Grenoble in Several serving points inside the Exhibition Hall

4.4 Emerging Solutions to Manage Energy/Performance Trad-Offs Along the Memory Hierarchy

Date: Tuesday 19 March 2013
Time: 17:00 - 18:30
Location / Room: Chartreuse

Chair:
Mladen Berekovic, Technical University of Braunschweig, DE

Co-Chair:
Cristina Silvano, Politecnico di Milano, IT

The session discusses emerging solutions to efficiently manage energy/performance trade-offs along the memory hierarchy from caches to secondary storage solutions. The first paper proposes a multiple access cache interface to provide low energy. The second paper introduces an efficient RAM management technique for NAND flash-based storage systems, while the third paper describes a data protection technique for NAND flash storage systems. The fourth paper proposes how to exploit sub-arrays inside a bank to improve the performance of Phase Change Memory, a promising alternative or supplement to DRAM.

TimeLabelPresentation Title
Authors
17:004.4.1MALEC: A MULTIPLE ACCESS LOW ENERGY CACHE
Authors:
Matthias Boettcher1, Giacomo Gabrielli2, Bashir M. Al-Hashimi1 and Danny Kershaw3
1University of Southampton, UK; 2ARM, UK; 3NXP Semiconductors, AT
Abstract
17:304.4.2TREEFTL: EFFICIENT RAM MANAGEMENT FOR HIGH PERFORMANCE OF NAND FLASH-BASED STORAGE SYSTEMS
Authors:
Chundong Wang and Weng-Fai Wong, National University of Singapore, SG
Abstract
18:004.4.3DA-RAID-5: A DISTURB AWARE DATA PROTECTION TECHNIQUE FOR NAND FLASH STORAGE SYSTEMS
Authors:
Jie Guo1, Wujie Wen1, Yaojun Zhang1, Sicheng Li2, Hai Li1 and Yiran Chen1
1University of Pittsburgh, US; 2Polytechnic Institute of New York University, US
Abstract
18:154.4.4EXPLOITING SUBARRAYS INSIDE A BANK TO IMPROVE PHASE CHANGE MEMORY PERFORMANCE
Authors:
Jianhui Yue and Yifeng Zhu, University of Maine, US
Abstract
18:30IP2-3, 697FUTURE OF GPGPU MICRO-ARCHITECTURAL PARAMETERS
Authors:
Cedric Nugteren, Gert-Jan van den Braak and Henk Corporaal, Eindhoven University of Technology, NL
Abstract
18:31IP2-4, 638SYNCHRONIZING CODE EXECUTION ON ULTRA-LOW-POWER EMBEDDED MULTI-CHANNEL SIGNAL ANALYSIS PLATFORMS
Authors:
Ahmed Yasir Dogan, Jeremy Constantin, Ruben Braojos Lopez, Giovanni Ansaloni, Andreas Burg and David Atienza, EPFL, CH
Abstract
18:32IP2-5, 329USING SYNCHRONIZATION STALLS IN POWER-AWARE ACCELERATORS
Authors:
Ali Jooya and Amirali Baniasadi, The University of Victoria, CA
Abstract
18:30End of session
Evening Reception offered by the City of Grenoble in Several serving points inside the Exhibition Hall

4.5 Device Identification and Protection

Date: Tuesday 19 March 2013
Time: 17:00 - 18:30
Location / Room: Meije

Chair:
Patrick Koeberl, Intel Labs, DE

Co-Chair:
Roel Maes, Intrinsic-ID, NL

System designers need secure building blocks for robust protection against physical and network attacks. This session presents the novel construction and implementation of physically unclonable functions as well as recent trends on counter-measure evaluation and realization.

TimeLabelPresentation Title
Authors
17:004.5.1COMPREHENSIVE ANALYSIS OF SOFTWARE COUNTERMEASURES AGAINST FAULT ATTACKS
Authors:
Nikolaus Theißing1, Dominik Merli2, Michael Smola3, Frederic Stumpf2 and Georg Sigl4
1Institute of Flight Systems,University of the Armed Forces, DE; 2Fraunhofer Research Institution for Applied and Integrated Security (AISEC), DE; 3Infineon Technologies, DE; 4Technische Universität München, DE
Abstract
17:304.5.2AN EDA-FRIENDLY PROTECTION SCHEME AGAINST SIDE-CHANNEL ATTACKS
Authors:
Ali Galip Bayrak1, Nikola Velickovic1, Francesco Regazzoni2, David Novo Bruna1, Philip Brisk3 and Paolo Ienne1
1EPFL, CH; 2Alari, CH; 3UC Riverside, US
Abstract
17:454.5.3DESIGN AND IMPLEMENTATION OF A GROUP-BASED RO PUF
Authors:
Chi-En Yin1, Gang Qu1 and Qiang Zhou2
1Univ. of Maryland, College Park, US; 2Tsinghua University, CN
Abstract
18:004.5.4CLOCKPUF: PHYSICAL UNCLONABLE FUNCTIONS BASED ON CLOCK NETWORKS
Authors:
Yida Yao1, Myungbo Kim1, Jianmin Li1, Igor L. Markov1 and Farinaz Koushanfar2
1University of Michigan, US; 2Rice University, US
Abstract
18:01IP2-6, 922MEMRISTOR PUFS: A NEW GENERATION OF MEMORY-BASED PHYSICALLY UNCLONABLE FUNCTIONS
Authors:
Unal Kocabas1, Patrick Koeberl2 and Ahmad-Reza Sadeghi3
1Technische Universität Darmstadt, DE; 2Intel Corporation, DE; 3Technische Universität Darmstadt and Fraunhofer SIT Darmstadt, DE
Abstract
18:02IP2-7, 856WIRELESS SENSOR NETWORK SIMULATION FOR SECURITY AND PERFORMANCE ANALYSIS
Authors:
Álvaro Díaz1, Pablo Sanchez1, Juan Sancho2 and Juan Rico2
1University of Cantabria, ES; 2TST, ES
Abstract
18:30End of session
Evening Reception offered by the City of Grenoble in Several serving points inside the Exhibition Hall

4.6 New Techniques for Test Pattern Generation

Date: Tuesday 19 March 2013
Time: 17:00 - 18:30
Location / Room: Bayard

Chair:
Sudhakar Reddy, University of Iowa, US

Co-Chair:
Matteo Sonza Reorda, Politecnico di Torino, IT

The session presents new test pattern generation methods for low power memory cells as well as for dealing with unknown values and delay faults.

TimeLabelPresentation Title
Authors
17:004.6.1(Best Paper Award Candidate)
ACCURATE QBF­-BASED TEST PATTERN GENERATION IN PRESENCE OF UNKNOWN VALUES
Authors:
Stefan Hillebrecht1, Michael A. Kochte2, Dominik Erb1, Hans-Joachim Wunderlich2 and Bernd Becker1
1University of Freiburg, DE; 2University of Stuttgart, DE
Abstract
17:304.6.2TEST SOLUTION FOR DATA RETENTION FAULTS IN LOW-POWER SRAMS
Authors:
Leonardo Henrique Bonet Zordan1, Alberto Bosio1, Patrick Girard1, Luigi Dilillo1, Aida Todri-Sanial1, Arnaud Virazel1 and Nabil Badereddine2
1LIRMM, FR; 2Intel Mobile Communications, FR
Abstract
18:004.6.3EFFICIENT SAT-BASED DYNAMIC COMPACTION AND RELAXATION FOR LONGEST SENSITIZABLE PATHS
Authors:
Matthias Sauer1, Sven Reimer1, Tobias Schubert1, Ilia Polian2 and Bernd Becker1
1University of Freiburg, DE; 2University of Passau, DE
Abstract
18:30IP2-8, 23PROCESS-VARIATION-AWARE IDDQ DIAGNOSIS FOR NANO-SCALE CMOS DESIGNS - THE FIRST STEP
Authors:
Chia-Ling (Lynn) Chang1, Charles H.-P. Wen1 and Jayanta Bhadra2
1National Chiao Tung University, TW; 2Freescale, US
Abstract
18:30End of session
Evening Reception offered by the City of Grenoble in Several serving points inside the Exhibition Hall

4.7 HOT TOPIC: Security Challenges in Automotive Hardware/Software Architecture Design

Date: Tuesday 19 March 2013
Time: 17:00 - 18:30
Location / Room: Les Bans

Organiser:
Samarjit Chakraborty, TU Munich, DE

Chair:
Jason Xue, City Univ. of Hong Kong, HK

Co-Chair:
Dip Goswami, TU Munich, DE

In modern cars, innovations are mainly driven by electronics and software. As a result, top-of-the-range vehicles comprise up to 100 Electronic Control Units (ECUs) and multiple heterogeneous buses connected via gateways. Various wireless communication protocols, like keyless entry systems or WiFi, connect the car with its surroundings while functionality in upcoming cars will be even more based on software with strong wireless connectivity. Similar to the first computers connected to the Internet, current automotive architectures are not designed for security which makes them highly vulnerable to attacks infiltrating the system. This session will focus on discussing this problem and on potential solutions from an embedded systems design perspective

TimeLabelPresentation Title
Authors
17:004.7.1SECURITY CHALLENGES IN AUTOMOTIVE HARDWARE/SOFTWARE ARCHITECTURE DESIGN
Authors:
Florian Sagstetter, Martin Lukasiewycz, Sebastian Steinhorst, Marko Wolf, Alexandre Bouard, William R. Harris, Somesh Jha, Thomas Peyrin, Axel Poschmann and Samarjit Chakraborty, TUM CREATE, SG
Abstract
17:304.7.2AUTOMOTIVE IP SECURITY: ENABLER FOR NEW CONNECTED FUNCTIONS IN CAR
Author:
Alexandre Bouard, BMW, DE
Abstract
18:004.7.3HACKING CARS: TAKING A LOOK BACK, A LOOK AT AND A LOOK AHEAD ON AUTOMOTIVE SECURITY
Authors:
Marko Wolf and Thomas Enderle, Escrypt, DE
Abstract
18:30End of session
Evening Reception offered by the City of Grenoble in Several serving points inside the Exhibition Hall

4.8 EXHIBITION THEATRE: Testimonials

Date: Tuesday 19 March 2013
Time: 17:00 - 18:30
Location / Room: Lesdigiueres (Exhibition Theatre)

Organiser:
Jürgen Haase, edacentrum, DE

Chair:
Jürgen Haase, edacentrum, DE

In this session industrial testimonials will offer engineers an insight into good working practices and state-of-the-art design methods of market leaders. This sessions features design centering of IO in 28nm FDSOI technology, SoC power integrity verification with focus on analogue/mixed signal macros, data management for future SoCs and evolutionary computation for validation, testing and design automation.

TimeLabelPresentation Title
Authors
17:004.8.1DESIGN CENTERING OF IO IN 28NM FDSOI TECHNOLOGY
Author:
Hubert Degoirat, STMicroelectronics, FR
Abstract
17:204.8.2USING APACHE REDHAWK FOR SOC POWER INTEGRITY VERIFICATION WITH FOCUS ON ANALOGUE/MIXED SIGNAL MACROS
Author:
Jack Kruppa, Infineon Technologies, DE
Abstract
17:404.8.3EVOLUTIONARY COMPUTATION FOR VALIDATION, TESTING AND DESIGN AUTOMATION
Authors:
Senad Durakovic and Aktan Burcin, Intel, US
Abstract
18:004.8.4DATA MANAGMENT IN FUTURE SOCS MADE EASY
Author:
Axel Jantsch, ELSIP, SE
Abstract
18:30End of session
Evening Reception offered by the City of Grenoble in Several serving points inside the Exhibition Hall

5.1 SPECIAL DAY on "High-Performance Low-Power Computing" HOT TOPIC - System Approaches to Energy-Efficiency

Date: Wednesday 20 March 2013
Time: 08:30 - 10:00
Location / Room: Oisans

Organiser:
Ahmed Jerraya, CEA-LETI-MINATEC, FR

Chair:
Patrick Blouet, ST Ericsson, FR

Co-Chair:
Ahmed Jerraya, CEA-LETI-MINATEC, FR

At system level, energy consumption optimisation may be the most rewarding. Different approaches may be applied to improve energy efficiency. This Hot-Topic Session explores both system architecture and applications to reach better energy efficiency.

TimeLabelPresentation Title
Authors
08:305.1.1EXPERIENCES WITH MOBILE PROCESSORS FOR ENERGY EFFICIENT HPC
Authors:
Alex Ramirez, Nikola Rajovic, Alejandro Rico, James Vipond, Isaac Gelado and Nikola Puzovic, BSC, ES
Abstract
08:505.1.2WHAT DESIGNS FOR COMING SUPERCOMPUTERS?
Author:
Xavier Vigouroux, Bull, FR
Abstract
09:105.1.3ENERGY-EFFICIENT IN-MEMORY DATABASE COMPUTING
Author:
Wolfgang Lehner, TU Dresden, DE
Abstract
09:305.1.4PERFORMANCE ANALYSIS OF HPC APPLICATIONS ON LOW-POWER EMBEDDED PLATFORMS
Authors:
Luka Stanisic1, Brice Videau1, Johan Cronsioe1, Augustin Degomme1, Vania Marangozova-Martin1, Arnaud Legrand1 and Jean-François Méhaut2
1CNRS/LIG, FR; 2UJF/LIG/CEA-Leti, FR
Abstract
10:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

5.2 PANEL: Can Energy Harvesting Deliver Enough Power for Automotive Electronics?

Date: Wednesday 20 March 2013
Time: 08:30 - 10:00
Location / Room: Belle-Etoile

Organisers:
Christoph Grimm, TU Kaiserslautern, DE
Tom Kazmierski, University of Southampton, UK

Chair:
Jürgen Haase, edacentrum, DE

Co-Chair:
Norbert Wehn, TU Kaiserslautern, DE

The panel will address upcoming technologies aimed at energy efficiency in energy harvester powered sensor networks for automotive applications. It will focus on the main challenge faced by the researchers working in this area: how to design efficiently analogue and digital automotive electronics powered by extremely low levels of harvested energy? The two industrial panelists will outline issues facing battery-less automotive sensor nodes powered by kinetic and thermal energy harvesters . The academic panelists will present currently being developed adaptive harvesters which can deliver maximum energy output in a changing environment, discuss techniques of virtual prototyping for ultra-low energy consumption and methods to analyse and optimise energy management and efficiency in automotive sensor nodes

10:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

5.3 Post-Silicon Debug Techniques

Date: Wednesday 20 March 2013
Time: 08:30 - 10:00
Location / Room: Stendahl

Chair:
Jaan Raik, Tallinn University of Technology, EE

Co-Chair:
Adrian Evans, iRoC Technologies, FR

It is becoming increasingly difficult to fully verify an SoC prior to tape-out resulting in more debug work occurring after first silicon. In the past, the techniques for post-silicon debug were largely ad-hoc. This session includes papers which highlight a new, emerging body of work which applies advanced algorithms to obtain optimized hardware for post-silicon debug. The first paper describes a new technique for selecting an optimal set of trace signals using a mixture of fast metrics and simulation profiling. In the second paper, the authors apply anomaly detection algorithms similar to those used for fraud detection to the automatic temporal and spatial localization of bugs. The third paper presents a low-area hardware block which can be used to reduce the volume of data that needs to be exported when dumping cache contents in the lab. The final paper tackles a slightly different, but very important aspect of silicon validation problem and proposes an innovative technique to perform BER estimation on high-speed links.

TimeLabelPresentation Title
Authors
08:305.3.1A HYBRID APPROACH FOR FAST AND ACCURATE TRACE SIGNAL SELECTION FOR POST-SILICON DEBUG
Authors:
Min Li and Azadeh Davoodi, University of Wisconsin - Madison, US
Abstract
09:005.3.2MACHINE LEARNING-BASED ANOMALY DETECTION FOR POST-SILICON BUG DIAGNOSIS
Authors:
Andrew DeOrio1, Qingkun Li2, Matthew Burgess1 and Valeria Bertacco1
1University of Michigan, US; 2University of Illinois at Urbana-Champaign, US
Abstract
09:155.3.3SPACE SENSITIVE CACHE DUMPING FOR POST-SILICON VALIDATION
Authors:
Sandeep Chandran, Smruti R. Sarangi and Preeti Ranjan Panda, Indian Institute of Technology Delhi, IN
Abstract
09:305.3.4FAST AND ACCURATE BER ESTIMATION METHODOLOGY FOR I/O LINKS BASED ON EXTREME VALUE THEORY
Authors:
Alessandro Cevrero1, Nestor Evmorfopoulos2, Charalampos Antoniadis2, Paolo Ienne1, Yusuf Leblebici1, Andreas Burg1 and George Stamoulis2
1EPFL, CH; 2University of Thessaly, GR
Abstract
10:00IP2-9, 481AUTOMATED DETERMINATION OF TOP LEVEL CONTROL SIGNALS
Authors:
Rohit Jain, Praveen Tiwari and Soumen Ghosh, Synopsys, IN
Abstract
10:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

5.4 Novel Approaches for Real-Time Architectures

Date: Wednesday 20 March 2013
Time: 08:30 - 10:00
Location / Room: Chartreuse

Chair:
Cristina Silvano, Politecnico di Milano, IT

Co-Chair:
Andreas Moshovos, University of Toronto , CA

This section focuses on new approaches for real-time architectures that go beyond classic static approaches. The first paper presents the first practical, effective, and efficient cache design that enables probabilistic worst-case execution time analysis. The second paper presents a novel architecture that enables fast and time-predictable computation for switched hybrid automata, a new modelling framework for power electronics applications. The third paper presents a conservative open-page memory controller policy that improves average-case performance without sacrificing worst-case time guarantees.

TimeLabelPresentation Title
Authors
08:305.4.1A CACHE DESIGN FOR PROBABILISTICALLY ANALYSABLE REAL-TIME SYSTEMS
Authors:
Leonidas Kosmidis1, Jaume Abella2, Eduardo Quiñones2 and Francisco J. Cazorla3
1Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES; 2Barcelona Supercomputing Center, ES; 3CSIC and BSC-CNS, ES
Abstract
09:005.4.2MARTHA: ARCHITECTURE FOR CONTROL AND EMULATION OF POWER ELECTRONICS AND SMART GRID SYSTEMS
Authors:
Michel Kinsy1, Omer Khan2, Ivan Celanovic1 and Srinivas Devadas1
1MIT, US; 2University of Connecticut, US
Abstract
09:305.4.3CONSERVATIVE OPEN-PAGE POLICY FOR MIXED TIME-CRITICALITY MEMORY CONTROLLERS
Authors:
Sven Goossens1, Benny Akesson2 and Kees Goossens1
1Eindhoven University of Technology, NL; 2Polytechnic Institute of Porto, PT
Abstract
10:00IP2-10, 274AN EFFICIENT AND FLEXIBLE HARDWARE SUPPORT FOR ACCELERATING SYNCHRONIZATION OPERATIONS ON THE STHORM MANY-CORE ARCHITECTURE
Authors:
Farhat Thabet, Yves Lhuillier, Caaliph Andriamisaina, Jean-Marc Philippe and Raphael David, CEA LIST, FR
Abstract
10:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

5.5 Error-Aware Adaptive Modern Computing Architectures

Date: Wednesday 20 March 2013
Time: 08:30 - 10:00
Location / Room: Meije

Chair:
Marco Santambroglio, Politecnico di Milano, IT

Co-Chair:
Marian Verhelst, Katholieke Universiteit Leuven, BE

This session covers the area of reliable and adaptive systems for practical computing applications. The scope of this session includes the development, optimization, and practical application mechanisms to compensate for aging and temperature, development of fault-tolerant systems, redundant designs and applications, reconfigurable systems and applications, static and dynamic reconfiguration techniques, context-aware applications, and self-adaptive architectures.

TimeLabelPresentation Title
Authors
08:305.5.1HOT-SWAPPING ARCHITECTURE WITH BACK-BIASED TESTING FOR MITIGATION OF PERMANENT FAULTS IN FUNCTIONAL UNIT ARRAY
Authors:
Zoltan E. Rakosi1, Masayuki Hiromoto1, Hiroshi Tsutsui1, Takashi Sato1, Yukihiro Nakamura2 and Hiroyuki Ochi1
1Kyoto University, JP; 2Ritsumeikan University, JP
Abstract
09:005.5.2VARIATION-TOLERANT OPENMP TASKING ON TIGHTLY-COUPLED PROCESSOR CLUSTERS
Authors:
Abbas Rahimi1, Andrea Marongiu2, Paolo Burgio2, Rajesh Gupta1 and Luca Benini2
1University of California, San Diego, US; 2University of Bologna, IT
Abstract
09:305.5.3ACCURATE AND EFFICIENT RELIABILITY ESTIMATION TECHNIQUES DURING ADL-DRIVEN EMBEDDED PROCESSOR DESIGN
Authors:
Zheng Wang, Kapil Singh, Chao Chen and Anupam Chattopadhyay, RWTH Aachen University, DE
Abstract
10:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

5.6 Advances in Mixed-Signal, RF, and MEMS testing

Date: Wednesday 20 March 2013
Time: 08:30 - 10:00
Location / Room: Bayard

Chair:
Salvador Mir, TIMA Laboratory, FR

Co-Chair:
Gildás Leger, University of Seville, ES

The first paper uses industrial data to demonstrate a technique for reducing the complexity of wafer-level testing of RF transceivers. The second paper presents the experimental validation of a defect detection and error-recovery technique for microfluidic bio-chips. The third paper shows defect-oriented testing in action for a large industrial mixed-signal circuit.

TimeLabelPresentation Title
Authors
08:305.6.1(Best Paper Award Candidate)
HANDLING DISCONTINUOUS EFFECTS IN MODELING SPATIAL CORRELATION OF WAFER-LEVEL ANALOG/RF TESTS
Authors:
Ke Huang1, Nathan Kupp2, John Carulli3 and Yiorgos Makris1
1UT Dallas, US; 2Yale University, US; 3Texas Instruments, US
Abstract
09:005.6.2FAULT DETECTION, REAL-TIME ERROR RECOVERY, AND EXPERIMENTAL DEMONSTRATION FOR DIGITAL MICROFLUIDIC BIOCHIPS
Authors:
Kai Hu, Bang-Ning Hsu, Andrew Madison, Krishnendu Chakrabarty and Richard Fair, Duke University, US
Abstract
09:305.6.3FAULT ANALYSIS AND SIMULATION OF LARGE SCALE INDUSTRIAL MIXED-SIGNAL CIRCUITS
Authors:
Ender Yilmaz1, Geoff Shofner1, LeRoy Winemberg1 and Sule Ozev2
1Freescale, US; 2Arizona State University, US
Abstract
10:00IP2-11, 682ELECTRICAL CALIBRATION OF SPRING-MASS MEMS CAPACITIVE ACCELEROMETERS
Authors:
Lingfei Deng1, Vinay Kundur1, Naveen Sai Jangala Naga1, Muhlis Kenan Ozel1, Ender Yilmaz1, Sule Ozev1, Bertan Bakkaloglu1, Sayfe Kiaei1, Divya Pratab2 and Tehmoor Dar2
1Arizona State University, US; 2Freescale, US
Abstract
10:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

5.7 Compilers and Software Synthesis for Embedded Systems

Date: Wednesday 20 March 2013
Time: 08:30 - 10:00
Location / Room: Les Bans

Chair:
Björn Franke, University of Edinburgh, UK

Co-Chair:
Heiko Falk, Ulm University, DE

This session covers a broad spectrum of topics in compilers, software synthesis, validation, and transformation. The first paper addresses communication optimization for kernels offloaded to accelerators. It is followed by a paper focussing on concurrency in a synchronous model of computation. The third paper deals with source-level cache modelling. The fourth paper proposes the management of heap data of tasks which are executed on a multi-core architecture with limited local memory.

TimeLabelPresentation Title
Authors
08:305.7.1(Best Paper Award Candidate)
OPTIMIZING REMOTE ACCESSES FOR OFFLOADED KERNELS: APPLICATION TO HIGH-LEVEL SYNTHESIS FOR FPGA
Authors:
Christophe Alias1, Alain Darte2 and Alexandru Plesco1
1INRIA, FR; 2CNRS, FR
Abstract
09:005.7.2SEQUENTIALLY CONSTRUCTIVE CONCURRENCY - A CONSERVATIVE EXTENSION OF THE SYNCHRONOUS MODEL OF COMPUTATION
Authors:
Reinhard von Hanxleden1, Michael Mendler2, Joaquin Aguado2, Björn Duderstadt1, Insa Fuhrmann1, Stephen Mercer3, Christian Motika1 and Owen O'Brien3
1Kiel University, DE; 2Bamberg University, DE; 3National Instruments, US
Abstract
09:305.7.3FAST AND ACCURATE CACHE MODELING IN SOURCE-LEVEL SIMULATION OF EMBEDDED SOFTWARE
Authors:
Zhonglei Wang and Jörg Henkel, Karlsruhe Institute of Technology, DE
Abstract
09:455.7.4AUTOMATIC AND EFFICIENT HEAP DATA MANAGEMENT FOR LIMITED LOCAL MEMORY MULTICORE ARCHITECTURES
Authors:
Ke Bai and Aviral Shrivastava, Arizona State University, US
Abstract
10:00IP2-12, 552SOFTWARE ENABLED WEAR-LEVELING FOR HYBRID PCM MAIN MEMORY ON EMBEDDED SYSTEMS
Authors:
Jingtong Hu1, Qingfeng Zhuge2, Chun Xue3, Wei-Che Tseng1 and Edwin Sha1
1University of Texas at Dallas, US; 2Chongqing University, CN; 3City University of Hong Kong, HK
Abstract
10:01IP2-13, 240PROBABILISTIC TIMING ANALYSIS ON CONVENTIONAL CACHE DESIGNS
Authors:
Leonidas Kosmidis1, Charlie Curtsinger2, Eduardo Quiñones3, Jaume Abella3, Emery Berger2 and Francisco Cazorla4
1Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES; 2University of Massachusetts Amherst, US; 3Barcelona Supercomputing Center, ES; 4Barcelona Supercomputing Center and IIIA-CSIC, ES
Abstract
10:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

IP2 Interactive Presentations

Date: Wednesday 20 March 2013
Time: 10:00 - 10:30
Location / Room: Exhibition Hall (espace accueil)

Interactive Presentations run simulatenously during a 30-minute slot. A poster associated to the IP paper is on display throughout the morning. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session, prior to the actual Interactive Presentation.

LabelPresentation Title
Authors
IP2-1AN EFFICIENT NETWORK ON-CHIP ARCHITECTURE BASED ON ISOLATING LOCAL AND NON-LOCAL COMMUNICATIONS
Authors:
Vahideh Akhlaghi1, Mehdi Kamal1, Ali Afzali-Kusha1 and Massoud Pedram2
1University of Tehran, IR; 2University of Southern California, US
Abstract
IP2-2SVR-NOC: A PERFORMANCE ANALYSIS TOOL FOR NETWORK-ON-CHIPS USING LEARNING-BASED SUPPORT VECTOR REGRESSION MODEL
Authors:
Zhiliang Qian1, Da-Cheng Juan2, Paul Bogdan2, Chi-Ying Tsui1, Diana Marculescu2 and Radu Marculescu2
1Hong Kong University of Science and Technology, HK; 2Carnegie Mellon University, US
Abstract
IP2-3FUTURE OF GPGPU MICRO-ARCHITECTURAL PARAMETERS
Authors:
Cedric Nugteren, Gert-Jan van den Braak and Henk Corporaal, Eindhoven University of Technology, NL
Abstract
IP2-4SYNCHRONIZING CODE EXECUTION ON ULTRA-LOW-POWER EMBEDDED MULTI-CHANNEL SIGNAL ANALYSIS PLATFORMS
Authors:
Ahmed Yasir Dogan, Jeremy Constantin, Ruben Braojos Lopez, Giovanni Ansaloni, Andreas Burg and David Atienza, EPFL, CH
Abstract
IP2-5USING SYNCHRONIZATION STALLS IN POWER-AWARE ACCELERATORS
Authors:
Ali Jooya and Amirali Baniasadi, The University of Victoria, CA
Abstract
IP2-6MEMRISTOR PUFS: A NEW GENERATION OF MEMORY-BASED PHYSICALLY UNCLONABLE FUNCTIONS
Authors:
Unal Kocabas1, Patrick Koeberl2 and Ahmad-Reza Sadeghi3
1Technische Universität Darmstadt, DE; 2Intel Corporation, DE; 3Technische Universität Darmstadt and Fraunhofer SIT Darmstadt, DE
Abstract
IP2-7WIRELESS SENSOR NETWORK SIMULATION FOR SECURITY AND PERFORMANCE ANALYSIS
Authors:
Álvaro Díaz1, Pablo Sanchez1, Juan Sancho2 and Juan Rico2
1University of Cantabria, ES; 2TST, ES
Abstract
IP2-8PROCESS-VARIATION-AWARE IDDQ DIAGNOSIS FOR NANO-SCALE CMOS DESIGNS - THE FIRST STEP
Authors:
Chia-Ling (Lynn) Chang1, Charles H.-P. Wen1 and Jayanta Bhadra2
1National Chiao Tung University, TW; 2Freescale, US
Abstract
IP2-9AUTOMATED DETERMINATION OF TOP LEVEL CONTROL SIGNALS
Authors:
Rohit Jain, Praveen Tiwari and Soumen Ghosh, Synopsys, IN
Abstract
IP2-10AN EFFICIENT AND FLEXIBLE HARDWARE SUPPORT FOR ACCELERATING SYNCHRONIZATION OPERATIONS ON THE STHORM MANY-CORE ARCHITECTURE
Authors:
Farhat Thabet, Yves Lhuillier, Caaliph Andriamisaina, Jean-Marc Philippe and Raphael David, CEA LIST, FR
Abstract
IP2-11ELECTRICAL CALIBRATION OF SPRING-MASS MEMS CAPACITIVE ACCELEROMETERS
Authors:
Lingfei Deng1, Vinay Kundur1, Naveen Sai Jangala Naga1, Muhlis Kenan Ozel1, Ender Yilmaz1, Sule Ozev1, Bertan Bakkaloglu1, Sayfe Kiaei1, Divya Pratab2 and Tehmoor Dar2
1Arizona State University, US; 2Freescale, US
Abstract
IP2-12SOFTWARE ENABLED WEAR-LEVELING FOR HYBRID PCM MAIN MEMORY ON EMBEDDED SYSTEMS
Authors:
Jingtong Hu1, Qingfeng Zhuge2, Chun Xue3, Wei-Che Tseng1 and Edwin Sha1
1University of Texas at Dallas, US; 2Chongqing University, CN; 3City University of Hong Kong, HK
Abstract
IP2-13PROBABILISTIC TIMING ANALYSIS ON CONVENTIONAL CACHE DESIGNS
Authors:
Leonidas Kosmidis1, Charlie Curtsinger2, Eduardo Quiñones3, Jaume Abella3, Emery Berger2 and Francisco Cazorla4
1Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES; 2University of Massachusetts Amherst, US; 3Barcelona Supercomputing Center, ES; 4Barcelona Supercomputing Center and IIIA-CSIC, ES
Abstract

UB05 Session 5

Date: Wednesday 20 March 2013
Time: 10:00 - 12:30
Location / Room: Booth 46, Exhibition

TimeLabelPresentation Title
Authors
10:00UB05.1COMBINING APPLICATION ADAPTIVITY AND SYSTEM-WIDE RESOURCE MANAGEMENT: A NOVEL APPROACH
Authors:
Edoardo Paone, Giuseppe Massari, Patrick Bellasi, William Fornaciari, Gianluca Palermo, Cristina Silvano and Vittorio Zaccaria, Politecnico di Milano, IT
Abstract
10:00UB05.2RODIN: MODELLING AND VERIFICATION TOOLSET
Author:
John Colley, University of Southampton, UK
Abstract
10:00UB05.3SYNTHORUS-2: AUTOMATIC PROTOTYPING ON FPGA FROM PSL
Authors:
Fatemeh Javaheri, Katell Morin‐Allory, Alexandre Porcher and Dominique Borrione, TIMA Lab, FR
Abstract
10:00UB05.4FUNCTIONAL VERIFICATION OF CUSTOM PROCESSORS USING AUTOMATED GENERATION OF VERIFICATION ENVIRONMENTS
Authors:
Marcela Šimková, Zdeněk Přikryl, Zdeněk Kotásek and Tomáš Hruška, Faculty of Information Technology, Brno University of Technology, CZ
Abstract
10:00UB05.5FPGA-BASED IP-CORES LIBRARY FOR ADVANCED IMAGE PROCESSING IN SPACE APPLICATIONS
Authors:
Pascal Trotta, Paolo Prinetto and Daniele Rolfo, Politecnico di Torino, IT
Abstract
10:00UB05.6ID.FIX: A SOFTWARE INFRASTRUCTURE FOR THE DESIGN OF EMBEDDED SYSTEMS USING FIXED-POINT ARITHMETIC
Authors:
Olivier Sentieys1, Daniel Ménard2 and Romuald Rocher3
1INRIA, FR; 2INSA Rennes, FR; 3University of Rennes 1, FR
Abstract
10:00UB05.7VUART: DEBUG OF A DESIGN EMBEDDING 24 MICRO-BLAZES ON A ZYNQ
Authors:
Pierre Bomel, Jean-Philippe Diguet and Kevin Martin, Université de Bretagne Sud, FR
Abstract
10:00UB05.8DATAFLOW-BASED ADAPTIVE MULTICORE EXECUTION ON A XILINX ZYNQ PLATFORM
Authors:
Julien Heulot, Yaset Oliva, Maxime Pelcat, Jean-François Nezan and Jean-Christophe Prevotet, INSA Rennes, IETR, FR
Abstract
10:00UB05.9ECA : AN INTEGRATED USER-FRIENDLY TOOL FOR EDUCATION OF COMPUTER ARITHMETIC
Authors:
Saba Amanollahi, Hamed Fatemi and Ghassem Jaberipur, Shahid Beheshti University, IR
Abstract
12:30End of session
Lunch Break in Ecrins
Sandwich lunch (Eat early for High-Performance Low-Power Computing - Energy Efficient Computing Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/7.0)

6.1 SPECIAL DAY on "High-Performance Low-Power Computing" EMBEDDED TUTORIAL - HW-SW Architecture Approaches to Energy-Efficiency

Date: Wednesday 20 March 2013
Time: 11:00 - 12:30
Location / Room: Oisans

Organiser:
Ahmed Jerraya, CEA-LETI-MINATEC, FR

Chair:
Agnès Fritsch, Thales Group, FR

Co-Chair:
Ahmed Jerraya, CEA-LETI-MINATEC, FR

Traditionally HW-SW interfaces are defined twice using two different models: one representing HW from a SW point of view, and one representing SW from a HW point of view. These separate views create a discontinuity in the design process and inevitably induces non-optimised designs from an energy-efficiency point of view. This embedded tutorial presents a HW view, a SW view, and an integrated HW-SW view to study the different approaches to energy efficiency

TimeLabelPresentation Title
Authors
11:006.1.1IC ARCHITECTURE APPROACHES TO ENERGY-EFFICIENCY
Author:
Thomas Pflueger, IBM, DE
Abstract
11:306.1.2SW ARCHITECTURE
Author:
David Rusling, Linaro, UK
Abstract
12:006.1.3HW-SW INTEGRATION FOR ENERGY-EFFICIENT/VARIABILITY-AWARE COMPUTING
Authors:
Gasser Ayad1, Andrea Acquaviva1, Enrico Macii1, Brahim Sahbi2 and Romain Lemaire2
1Politecnico di Torino, IT; 2CEA-Leti, FR
Abstract
12:30End of session
Lunch Break in Ecrins
Sandwich lunch (Eat early for High-Performance Low-Power Computing - Energy Efficient Computing Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/7.0)

6.2 HOT TOPIC: Emerging Nanoscale Devices: A Booster for High Performance Computing

Date: Wednesday 20 March 2013
Time: 11:00 - 12:30
Location / Room: Belle-Etoile

Organisers:
Giovanni De Micheli, EPFL, CH
Pierre-Emmanuel Gaillardon, EPFL, CH

Chair:
Giovanni De Micheli, EPFL, CH

Co-Chair:
Ahmed Jerraya, CEA, LETI, Minatec, FR

As the semiconductor industry advances into the era of nanotechnology, the devices are expected to be scaled down to their physical and economic limits. These limitations require the industry to explore the use of novel materials and device structures able to replace the current CMOS transistors within the next few years. In this session, we elaborate on novel and emerging technologies, from advanced Silicon devices to carbon electronics, that can help pushing the Moore's Law beyond. We will detail the novel physical design techniques, architectural organizations and CAD tools identified to keep improving the performance of the computation structures, while maintaining an acceptable yield.

TimeLabelPresentation Title
Authors
11:006.2.1NEAR-THRESHOLD VOLTAGE DESIGN IN NANOSCALE CMOS
Author:
Vivek De, Intel, US
Abstract
11:226.2.2ULTRA-WIDE VOLTAGE RANGE DESIGNS IN FULLY-DEPLETED SILICON-ON-INSULATOR FET
Authors:
Edith Beigné1, Philippe Flatresse2, Bastien Giraud1, Jean-Philippe Noel2, Olivier Thomas1, Anuj Grover2, Thomas Benoist1, Fady Abouzeid2, Yvain Thonnart1, Bertrand Pelloux-Prayer2, Sébastien Bernard1, Sylvain Clerc2, Guillaume Moritz1, Philippe Roche2, Olivier Billoint1, Julien Le Coz2, Yves Maneglia1, Sylvain Engels2, Alexandre Valentian1 and Robin Wilson2
1CEA-Leti, Minatec, FR; 2STMicroelectronics, FR
Abstract
11:456.2.3CARBON NANOTUBE CIRCUITS: OPPORTUNITIES AND CHALLENGES
Authors:
Hai Wei, Max Shulaker, Gage Hills, Hong-Yu Chen, Chi-Shuen Lee, Luckshitha Liyanage, Jie Jerry Zhang, H.-S. Philip Wong and Subhasish Mitra, Stanford University, US
Abstract
12:076.2.4VERTICALLY-STACKED DOUBLE-GATE NANOWIRE FETS WITH CONTROLLABLE POLARITY: FROM DEVICES TO REGULAR ASICS
Authors:
Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici and Giovanni De Micheli, EPFL, CH
Abstract
12:30End of session
Lunch Break in Ecrins
Sandwich lunch (Eat early for High-Performance Low-Power Computing - Energy Efficient Computing Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/7.0)

6.3 Verification and Simulation Support for Architecture

Date: Wednesday 20 March 2013
Time: 11:00 - 12:30
Location / Room: Stendahl

Chair:
Valeria Bertacco, University of Michigan, US

Co-Chair:
Elena Vatajelu, LIRMM, FR

With processor architectures becoming increasingly complex and concurrent, new verification ideas are needed to rescue them from being bug-ridden. This session addresses a number of key issues in this domain: simulation performance, correctness of concurrency, and of the models used to validate the software running on them. The session presents solutions to boost the performance of architectural simulators and cache simulation and to effectively verify memory transactions with respect to consistency.

TimeLabelPresentation Title
Authors
11:006.3.1ON-THE-FLY VERIFICATION OF MEMORY CONSISTENCY WITH CONCURRENT RELAXED SCOREBOARDS
Authors:
Leandro S. Freitas, Eberle A. Rambo and Luiz C. V. dos Santos, Federal University of Santa Catarina, BR
Abstract
11:306.3.2FAST CACHE SIMULATION FOR HOST-COMPILED SIMULATION OF EMBEDDED SOFTWARE
Authors:
Kun Lu, Daniel Mueller-Gritschneder and Ulf Schlichtmann, Technische Universität München, DE
Abstract
12:006.3.3A CRITICAL-SECTION-LEVEL TIMING SYNCHRONIZATION APPROACH FOR DETERMINISTIC MULTI-CORE INSTRUCTION-SET SIMULATIONS
Authors:
Fan-Wei Yu, Bo-Han Zeng, Yu-Hung Huang, Hsin-I Wu, Che-Rung Lee and Ren-Song Tsay, National Tsing Hua University, TW
Abstract
12:156.3.4MULTI-LEVEL PHASE ANALYSIS FOR SAMPLING SIMULATION
Authors:
Jiaxin Li1, Weihua Zhang1, Haibo Chen2 and Binyu Zang1
1Fudan University, CN; 2Shanghai Jiaotong University, CN
Abstract
12:30IP3-1, 232HYPERVISED TRANSIENT SPICE SIMULATIONS OF LARGE NETLISTS & WORKLOADS ON MULTI-PROCESSOR SYSTEMS
Authors:
Grigorios Lyras, Dimitrios Rodopoulos, Antonis Papanikolaou and Dimitrios Soudris, NTUA-ECE-MicroLab, GR
Abstract
12:30End of session
Lunch Break in Ecrins
Sandwich lunch (Eat early for High-Performance Low-Power Computing - Energy Efficient Computing Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/7.0)

6.4 Design Space Exploration for Application Specific Architectures

Date: Wednesday 20 March 2013
Time: 11:00 - 12:30
Location / Room: Chartreuse

Chair:
Andreas Moshovos, University of Toronto , CA

Co-Chair:
Georgi Gaydadjiev, Chalmers University of Technology, SE

This session presents a collection of papers that advances design space exploration for application-specific customization. The first paper proposes an analytical meta-model for area and delay to predict the quality of the design points in co-processor synthesis leading to significant speed-up in the design space exploration process. The second paper designs an application-specific customization of memory hierarchy for multi-view video coding. The final paper in this session employs an analytical model to reduce the number of cycle-accurate simulations for exploration of many-core embedded platforms.

TimeLabelPresentation Title
Authors
11:006.4.1A META-MODEL ASSISTED COPROCESSOR SYNTHESIS FRAMEWORK FOR COMPILER/ARCHITECTURE PARAMETERS CUSTOMIZATION
Authors:
Sotirios Xydis, Gianluca Palermo, Vittorio Zaccaria and Cristina Silvano, Politecnico di Milano, IT
Abstract
11:306.4.2ENERGY-EFFICIENT MEMORY HIERARCHY FOR MOTION AND DISPARITY ESTIMATION IN MULTIVIEW VIDEO CODING
Authors:
Felipe Sampaio1, Bruno Zatt2, Muhammad Shafique2, Luciano Agostini3, Sergio Bampi1 and Jörg Henkel2
1Federal University of Rio Grande do Sul, BR; 2Karlsruhe Institute of Technology, DE; 3Federal University of Pelotas, BR
Abstract
12:006.4.3IMPROVING SIMULATION SPEED AND ACCURACY FOR MANY-CORE EMBEDDED PLATFORMS WITH ENSEMBLE MODELS
Authors:
Edoardo Paone1, Nazanin Vahabi1, Vittorio Zaccaria1, Cristina Silvano1, Diego Melpignano2, Germain Haugou2 and Thierry Lepley2
1Politecnico di Milano, IT; 2STMicroelectronics, FR
Abstract
12:30IP3-2, 420STATICALLY-SCHEDULED APPLICATION-SPECIFIC PROCESSOR DESIGN: A CASE-STUDY ON MMSE MIMO EQUALIZATION
Authors:
Mostafa Rizk1, Amer Baghdadi2, Michel Jezequel2, Yasser Mohana3 and Youssef Atat3
1Telecom Bretagne, Lebanese University, FR; 2Telecom Bretagne, FR; 3Lebanese University, LB
Abstract
12:31IP3-3, 795EXPLORING RESOURCE MAPPING POLICIES FOR DYNAMIC CLUSTERING ON NOC-BASED MPSOCS
Authors:
Gustavo Girao, Thiago Santini and Flavio Wagner, Federal University of Rio Grande do Sul, BR
Abstract
12:32IP3-4, 569CHARACTERIZING THE PERFORMANCE BENEFITS OF FUSED CPU/GPU SYSTEMS USING FUSIONSIM
Authors:
Vitaly Zakharenko1, Tor Aamodt2 and Andreas Moshovos1
1University of Toronto, CA; 2University of British Columbia, CA
Abstract
12:30End of session
Lunch Break in Ecrins
Sandwich lunch (Eat early for High-Performance Low-Power Computing - Energy Efficient Computing Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/7.0)

6.5 Reliable Multi-Processor Computing Systems Design

Date: Wednesday 20 March 2013
Time: 11:00 - 12:30
Location / Room: Meije

Chair:
Jose Ayala, Complutense University of Madrid, ES

Co-Chair:
Christian Pilato, Politecnico di Milano, IT

This session tackles the problems of task mapping and allocation for latest multi-processor systems under possible error conditions. The first paper deals with task mapping to maximize the correct operation of multi-processor architectures under reliability constrained setups. The second paper proposes a new scheduling framework for processing systems that can adapt to different fault tolerance requirements. The third paper explores methods to use coarse-grained reconfigurable architectures in order to guarantee reliable system-level behavior, and the fourth paper explores the development of a configurable soft-error resilience approach to achieve reliable specific instruction-set processing architectures.

TimeLabelPresentation Title
Authors
11:006.5.1(Best Paper Award Candidate)
RELIABILITY-DRIVEN TASK MAPPING FOR LIFETIME EXTENSION OF NETWORKS-ON-CHIP BASED MULTIPROCESSOR SYSTEMS
Authors:
Anup Das, Akash Kumar and Bharadwaj Veeravalli, National University of Singapore, SG
Abstract
11:306.5.2A WORK-STEALING SCHEDULING FRAMEWORK SUPPORTING FAULT TOLERANCE
Authors:
Yizhuo Wang, Weixing Ji, Feng Shi and Qi Zuo, Beijing Institute of Technology, CN
Abstract
12:006.5.3A COST-EFFECTIVE SELECTIVE TMR FOR HETEROGENEOUS COARSE-GRAINED RECONFIGURABLE ARCHITECTURES BASED ON DFG-LEVEL VULNERABILITY ANALYSIS
Authors:
Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi and Takashi Sato, Kyoto University, JP
Abstract
12:156.5.4CSER: HW/SW CONFIGURABLE SOFT-ERROR RESILIENCY FOR APPLICATION SPECIFIC INSTRUCTION-SET PROCESSORS
Authors:
Tuo Li1, Muhammad Shafique2, Semeen Rehman2, Swarnalatha Radhakrishnan1, Roshan Ragel1, Jude Angelo Ambrose1, Jörg Henkel2 and Sri Parameswaran1
1University of New South Wales, AU; 2Karlsruhe Institute of Technology, DE
Abstract
12:30IP3-5, 101RELIABILITY ANALYSIS FOR INTEGRATED CIRCUIT AMPLIFIERS USED IN NEURAL MEASUREMENT SYSTEMS
Authors:
Nico Hellwege, Nils Heidmann, Dagmar Peters-Drolshagen and Steffen Paul, University of Bremen, DE
Abstract
12:31IP3-6, 271ON-LINE TESTING OF PERMANENT RADIATION EFFECTS IN RECONFIGURABLE SYSTEMS
Authors:
Luca Cassano1, Dario Cozzi2, Sebastian Korf2, Jens Hagemeyer2, Mario Porrmann2 and Luca Sterpone3
1University of Pisa, IT; 2Bielefeld University, DE; 3Politecnico di Torino, IT
Abstract
12:32IP3-7, 426AN APPROACH FOR REDUNDANCY IN FLEXRAY NETWORKS USING FPGA PARTIAL RECONFIGURATION
Authors:
Shanker Shreejith1, Kizheppatt Vipin1, Suhaib A Fahmy1 and Martin Lukasiewycz2
1Nanyang Technological University, SG; 2TUM CREATE, SG
Abstract
12:30End of session
Lunch Break in Ecrins
Sandwich lunch (Eat early for High-Performance Low-Power Computing - Energy Efficient Computing Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/7.0)

6.6 HOT TOPIC: Energy-Efficient Design and Test Techniques for Future Multi-Core Systems

Date: Wednesday 20 March 2013
Time: 11:00 - 12:30
Location / Room: Bayard

Organiser:
Krishnendu Chakrabarty, Duke University, US

Chair:
Mehdi Tahoori, Karlsruhe Institute of Technology, DE

Co-Chair:
Paul Pop, Technical University of Denmark, DK

In this hot topic session, the speakers will describe new, far-reaching design methods and test techniques that achieve energy efficiency and low defect escapes in massively integrated single-chip computing platforms. By integrating design, design automation, and test content, this session will provide a holistic view of multi-core systems to DATE attendees.

TimeLabelPresentation Title
Authors
11:006.6.1ENERGY-EFFICIENT MULTICORE CHIP DESIGN THROUGH CROSS-LAYER APPROACH
Authors:
Paul Wettin1, Jacob Murray1, Partha Pratim Pande1, Behrooz Shirazi1 and Amlan Ganguly2
1Washington State University, US; 2Rochester Institute of Technology, US
Abstract
11:206.6.2BREAKING THE ENERGY BARRIER IN FAULT-TOLERANT CACHES FOR MULTICORE SYSTEMS
Authors:
Paul Ampadu1, Meilin Zhang1 and Vladimir Stojanovic2
1University of Rochester, US; 2Massachusetts Institute of Technology, US
Abstract
11:406.6.3TESTING FOR SOCS WITH ADVANCED STATIC AND DYNAMIC POWER-MANAGEMENT CAPABILITIES
Authors:
Chrysovalantis Kavousianos1 and Krishnendu Chakrabarty2
1University of Ioannina, GR; 2Duke University, US
Abstract
12:006.6.4TOWARDS ADAPTIVE TEST OF MULTI-CORE RF SOCS
Authors:
Rajesh Mittal, Lakshmanan Balasubramanian, Chethan Kumar Y. B., V. R Devanathan, Mudasir Kawoosa and Rubin A. Parekhji, Texas Instruments, IN
Abstract
12:30End of session
Lunch Break in Ecrins
Sandwich lunch (Eat early for High-Performance Low-Power Computing - Energy Efficient Computing Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/7.0)

6.7 Model-Based Design and Verification for Embedded Systems

Date: Wednesday 20 March 2013
Time: 11:00 - 12:30
Location / Room: Les Bans

Chair:
Wang Yi', Uppsala University, SE

Co-Chair:
Saddek Bensalem, Verimag, FR

This session includes four papers. The first and the third papers present two different techniques to solve design optimization problems for systems with multiple conflicting constraints on timing, buffer, and energy. The second and the last papers address issues on performance bottlenecks and weakly real-time guarantees in multi-core systems as well as real-time systems in the presents of sporadic workload bursts.

TimeLabelPresentation Title
Authors
11:006.7.1(Best Paper Award Candidate)
A SATISFIABILITY APPROACH TO SPEED ASSIGNMENT FOR DISTRIBUTED REAL-TIME SYSTEMS
Authors:
Pratyush Kumar, Devesh B. Chokshi and Lothar Thiele, ETH Zurich, CH
Abstract
11:306.7.2DATA MINING MPSOC SIMULATION TRACES TO IDENTIFY CONCURRENT MEMORY ACCESS PATTERNS
Authors:
Sofiane Lagraa, Alexandre Termier and Frédéric Pétrot, Grenoble Institute of Technology, FR
Abstract
12:006.7.3MODEL-BASED ENERGY OPTIMIZATION OF AUTOMOTIVE CONTROL SYSTEMS
Authors:
Joost-Pieter Katoen1, Thomas Noll1, Thomas Santen2, Dirk Seifert2 and Hao Wu1
1RWTH Aachen University, DE; 2Microsoft Research, DE
Abstract
12:156.7.4FORMAL ANALYSIS OF SPORADIC BURSTS IN REAL-TIME SYSTEMS
Authors:
Sophie Quinton, Mircea Negrean and Rolf Ernst, TU Braunschweig, DE
Abstract
12:30End of session
Lunch Break in Ecrins
Sandwich lunch (Eat early for High-Performance Low-Power Computing - Energy Efficient Computing Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/7.0)

6.8 EXHIBITION THEATRE: Silicon Europe - Leading European Regions Join Forces

Date: Wednesday 20 March 2013
Time: 11:00 - 12:30
Location / Room: Lesdigiueres (Exhibition Theatre)

Organiser:
Jürgen Haase, edacentrum, DE

Chair:
Thomas Reppe, Silicon Saxony, DE

Four of the leading European micro- and nanoelectronics regions are joining their research, development and production expertise to form the transnational, research-driven cluster "Silicon Europe - The Leaders for Energy Efficient ICT Electronics". The cluster partners from Germany, Belgium, France and the Netherlands are linked by a common goal: They aim to secure and expand Europe's position as the world's leading center for energy efficient micro- and nanoelectronics and information and communications technology (ICT). In order to reach this goal, Silicon Saxony (Dresden/Germany), DSP Valley (Belgium), Minalogic (Grenoble/France) and High Tech NL (Eindhoven/Netherlands) are cooperating in research, development and business expertise. Together they represent about 800 research institutes and companies, which account for more than 150,000 jobs; among the companies are global market leaders such as Philips, NXP, Globalfoundries, Infineon, STMicroelectronics, Schneider Electric und Thales. This makes Silicon Europe one of the largest technology clusters of the world.

TimeLabelPresentation Title
Authors
11:006.8.1SILICON EUROPE - CLUSTER ALLIANCE FOR EUROPEAN MICRO- AND NANOELECTRONICS INDUSTRY - TOPICS, CHALLENGES, OPPORTUNITIES
Author:
Thomas Reppe, Silicon Saxony, DE
Abstract
11:206.8.2MINALOGIC: FROM RESEARCH TO INDUSTRY
Author:
Jean Chabbal, Minalogic, FR
Abstract
11:356.8.3SILICON SAXONY - A HIGH TECH LOCATION OF GREAT DIVERSITY
Author:
Andreas Brüning, Silicon Saxony, DE
Abstract
11:506.8.4THE DUTCH SEMICON CLUSTER: A COMPLETE VALUE CHAIN
Author:
Ben van der Zon, High Tech NL, NL
Abstract
12:056.8.5DSP VALLEY - REGION OF EXCELLENCE IN EMBEDDED SIGNAL PROCESSING SYSTEMS DESIGN
Author:
Peter Simkens, DSP Valley, BE
Abstract
12:206.8.6PANEL
Authors:
Thomas Reppe1, Jean Chabbal2, Andreas Brüning1, Ben van der Zon3 and Peter Simkens4
1Silicon Saxony, DE; 2Minalogic, FR; 3High Tech NL, NL; 4DSP Valley, BE
Abstract
12:30End of session
Lunch Break in Ecrins
Sandwich lunch (Eat early for High-Performance Low-Power Computing - Energy Efficient Computing Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/7.0)

UB06 Session 6

Date: Wednesday 20 March 2013
Time: 12:30 - 14:30
Location / Room: Booth 46, Exhibition

TimeLabelPresentation Title
Authors
12:30UB06.1LIPS: AN IDE FOR SYSTEM DESIGN BASED ON NATURAL LANGUAGE PROCESSING
Authors:
Mathias Soeken, Oliver Keszöcze, Eugen Kuksa and Rolf Drechsler, University of Bremen, DE
Abstract
12:30UB06.2RODIN: MODELLING AND VERIFICATION TOOLSET
Author:
John Colley, University of Southampton, UK
Abstract
12:30UB06.3TACP: TEST AND CHARACTERIZATION PLATFORM
Authors:
Muhammad Elrabaa and Amran Al-Aghbari, King Fahd University of Petroleum and Minerals, SA
Abstract
12:30UB06.4TCPA: RESOURCE-AWARE VIDEO PROCESSING ON TIGHTLY-COUPLED PROCESSOR ARRAYS
Authors:
Vahid Lari, Srinivas Boppu, Frank Hannig, Shravan Muddassani, Boris Kuzmin and Jürgen Teich, University of Erlangen-Nuremberg, DE
Abstract
12:30UB06.5MICROTESK: ADVANCED TEST PROGRAM GENERATOR FOR MICROPROCESSORS
Authors:
Andrei Tatarnikov and Alexander Kamkin, Institute for System Programming of the Russian Academy of Sciences (ISP RAS), RU
Abstract
12:30UB06.6SIMULINK-BASED HIGH LEVEL HARDWARE SYNTHESIS AND DESIGN SPACE EXPLORATION
Authors:
Shahzad Ahmad Butt and Luciano Lavagno, Politecnico di Torino, IT
Abstract
12:30UB06.7FT-UNSHADES2 A FLEXIBLE FAULT INJECTION FRAMEWORK
Authors:
Juan Mogollón and Hipolito Guzman, University of Sevilla, ES
Abstract
12:30UB06.8RELIABILITY EVALUATION OF HETEROGENOUS SYSTEMS
Authors:
Daniel Froß, Christian Pätz, Marko Rößler, Daniel Kriesten and Ulrich Heinkel, TU Chemnitz, DE
Abstract
12:30UB06.9EF3S: EVALUATION FRAMEWORK FOR FLASH-BASED SYSTEMS
Authors:
Marco Indaco, Salvatore Galfano, Stefano Di Carlo and Paolo Prinetto, Politecnico di Torino, IT
Abstract
14:30End of session
16:00Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

7.0 Special Day Keynote on "High-Performance Low-Power Computing"

Date: Wednesday 20 March 2013
Time: 13:30 - 14:00
Location / Room: Oisans

TimeLabelPresentation Title
Authors
13:306.1.2.1ENERGY-EFFICIENT COMPUTING
Author:
John Goodacre, ARM, UK
Abstract: Since the first mobile computer, power efficiency was a key measure for success. As the need for performance ever increases, the energy cost of performance has metric well beyond just the life of the battery in mobile. Energy efficiency is now the driver in most consumer products, the compute density of a server, and has become the primary limit in the delivery of high performance. During this talk we will consider the various power related limitations of compute while discovering how the techniques and new capabilities introduced into mobile computing also bring the flexibility to address the limitations of the traditional computing approach.
14:00End of session
16:00Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

7.1 SPECIAL DAY on "High-Performance Low-Power Computing" HOT TOPIC - Many-Core SoC Approaches to Energy-Efficiency

Date: Wednesday 20 March 2013
Time: 14:30 - 16:00
Location / Room: Oisans

Organiser:
Ahmed Jerraya, CEA-LETI-MINATEC, FR

Chair:
Marc Duranton, CEA, FR

Co-Chair:
Ahmed Jerraya, CEA-LETI-MINATEC, FR

The evolution of the semiconductor industry is allowing intensive computing on a single chip through heterogeneous and homogeneous architectures. This increase in compute density on a single chip is both a threat and an opportunity for energy-efficiency. This Hot-Topic Session presents different many-core SoC approaches to improve energy-efficiency.

TimeLabelPresentation Title
Authors
14:307.1.1DEVELOPMENT OF LOW POWER MANY-CORE SOC FOR MULTIMEDIA APPLICATIONS
Authors:
Takashi Miyamori, Hui Xu, Takeshi Kodaka, Hiroyuki Usui, Toru Sano and Jun Tanabe, Toshiba, JP
Abstract
14:507.1.2SOC LOW-POWER PRACTICES FOR WIRELESS APPLICATIONS
Authors:
Nicolas Darbel and Stephane Lecomte, ST-Ericsson, FR
Abstract
15:107.1.3FUTURE LOW-POWER SOC
Author:
Koji Inoue, Kyushu University, JP
Abstract
15:307.1.43D INTEGRATION FOR POWER-EFFICIENT COMPUTING
Authors:
Denis Dutoit, Eric Guthmuller and Ivan Miro-Panades, CEA-Leti, FR
Abstract
16:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

7.2 Formal Verification Algorithms and Models

Date: Wednesday 20 March 2013
Time: 14:30 - 16:00
Location / Room: Belle-Etoile

Chair:
Christoph Scholl, University of Freiburg, DE

Co-Chair:
Jason Baumgartner, IBM, US

The session covers an application of formal methods to the verification of Transactional Memories as well as techniques to broaden the scope of modern core verification techniques. The first paper presents a formal model for Hybrid Transactional Memories and a correctness proof based on this formalization. The second paper extends IC3 / PDR (a recent, highly successful method for model checking by incrementally building inductive invariants) from Boolean formulas to quantifier-free formulas with bit vectors. Finally, the third paper presents a method for semi-canonical labeling And Inverter Graphs which aims at speeding-up sequential verification by identifying isomorphic structures.

TimeLabelPresentation Title
Authors
14:307.2.1VERIFYING SAFETY AND LIVENESS FOR THE FLEXTM HYBRID TRANSACTIONAL MEMORY
Authors:
Parosh Abdulla1, Sandhya Dwarkadas2, Ahmed Rezine3, Arrvindh Shriraman4 and Yunyun Zhu1
1Uppsala University, SE; 2Rochester University, US; 3Linköping University, SE; 4Simon Fraser University, CA
Abstract
15:007.2.2QF_BV MODEL CHECKING WITH PROPERTY DIRECTED REACHABILITY
Authors:
Tobias Welp1 and Andreas Kuehlmann2
1University of California, Berkeley, US; 2Coverity, US
Abstract
15:307.2.3A SEMI-CANONICAL FORM FOR SEQUENTIAL AIGS
Authors:
Alan Mishchenko1, Niklas Een1, Robert Brayton1, Michael Case2, Pankaj Chauhan2 and Nikhil Sharma2
1University of California, Berkeley, US; 2Calypto Design Systems, US
Abstract
16:00IP3-8, 651FAST CONE-OF-INFLUENCE COMPUTATION AND ESTIMATION IN PROBLEMS WITH MULTIPLE PROPERTIES
Authors:
Carmelo Loiacono1, Marco Palena1, Paolo Pasini1, Denis Patti1, Stefano Quer1, Stefano Ricossa1, Danilo Vendraminetto1 and Jason Baumgartner2
1Politecnico di Torino, IT; 2IBM Research, US
Abstract
16:01IP3-9, 488USING CUBES OF NON-STATE VARIABLES WITH PROPERTY DIRECTED REACHABILITY
Authors:
John Backes and Marc Riedel, University of Minnesota, US
Abstract
16:02IP3-10, 214BRIDGING THE GAP BETWEEN DUAL PROPAGATION AND CNF-BASED QBF SOLVING
Authors:
Alexandra Goultiaeva1, Martina Seidl2 and Armin Biere2
1University of Toronto, CA; 2Johannes Kepler University, AT
Abstract
16:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

7.3 Dynamic Reconfiguration

Date: Wednesday 20 March 2013
Time: 14:30 - 16:00
Location / Room: Stendahl

Chair:
Diana Goehringer, Karlsruhe Institute of Technology, DE

Co-Chair:
Fabrizio Ferrandi, Politecnico di Milano, IT

In this session dynamic reconfiguration techniques are presented and exploited in new tools and hardware architectures. The first paper deals with an algorithm for prefetching dynamic partial bit streams in hardware platforms that support dynamic partial reconfiguration.The second paper introduces a new tool performing dynamic circuit synthesis for designing reconfigurable multi-mode circuits. The two short papers propose first a generic binary format for VLIW processors with adaptive issue-widths and second a modular IP-core based approach to simplify the design of run-time reconfigurable systems.

TimeLabelPresentation Title
Authors
14:307.3.1(Best Paper Award Candidate)
DYNAMIC CONFIGURATION PREFETCHING BASED ON PIECEWISE LINEAR PREDICTION
Authors:
Adrian Lifa, Petru Eles and Zebo Peng, Linköping University, SE
Abstract
15:007.3.2AN AUTOMATIC TOOL FLOW FOR THE COMBINED IMPLEMENTATION OF MULTI-MODE CIRCUITS
Authors:
Brahim Al Farisi1, Karel Bruneel1, João M. P. Cardoso2 and Dirk Stroobandt1
1University of Ghent, BE; 2University of Porto, PT
Abstract
15:307.3.3SUPPORT FOR DYNAMIC ISSUE WIDTH IN VLIW PROCESSORS USING GENERIC BINARIES
Authors:
Anthony Brandon and Stephan Wong, TUDelft, NL
Abstract
15:457.3.4THE RECOBLOCK SOC PLATFORM:A FLEXIBLE ARRAY OF REUSABLE RUN-TIME-RECONFIGURABLE IP-BLOCKS
Authors:
Byron Navas, Ingo Sander and Johnny Öberg, KTH Royal Institute of Technology, SE
Abstract
16:00IP3-11, 952DANCE: DISTRIBUTED APPLICATION-AWARE NODE CONFIGURATION ENGINE IN SHARED RECONFIGURABLE SENSOR NETWORKS
Authors:
Chih-Ming Hsieh, Zhonglei Wang and Jörg Henkel, Karlsruhe Institute of Technology, DE
Abstract
16:01IP3-12, 499HYBRID INTERCONNECT DESIGN FOR HETEROGENEOUS HARDWARE ACCELERATORS
Authors:
Cuong Pham-Quoc1, Jan Heisswolf2, Stephan Werner2, Zaid Al-Ars1, Jürgen Becker2 and Koen Bertels1
1Delft University of Technology, NL; 2Karlsruhe Institute of Technology, DE
Abstract
16:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

7.4 Emerging Memory

Date: Wednesday 20 March 2013
Time: 14:30 - 16:00
Location / Room: Chartreuse

Chair:
Ian O'Connor, Lyon Institute of Nanotechnology, FR

Co-Chair:
Siddharth Garg, University of Waterloo, CA

This session has three papers discussing STT-MRAM based Cache, Dual-Port Acces STT-MRAM, and NAND FLASH storage with PRAM/DRAM Hybrid Buffer.

TimeLabelPresentation Title
Authors
14:307.4.1(Best Paper Award Candidate)
OAP: AN OBSTRUCTION-AWARE CACHE MANAGEMENT POLICY FOR STT-RAM LAST-LEVEL CACHES
Authors:
Jue Wang, Xiangyu Dong and Yuan Xie, Pennsylvania State University, US
Abstract
15:007.4.2STT-RAM CELL DESIGN SUPPORTING DUAL-PORT ACCESSES
Authors:
Xiuyuan Bi1, Mohamed Anis Weldon2 and Hai Li1
1University of Pittsburgh, US; 2Polytechnic Institute of New York University, US
Abstract
15:307.4.3LOW COST POWER FAILURE PROTECTION FOR MLC NAND FLASH STORAGE SYSTEMS WITH PRAM/DRAM HYBRID BUFFER
Authors:
Jie Guo, Jun Yang, Youtao Zhang and Yiran Chen, University of Pittsburgh, US
Abstract
16:00IP3-13, 603SPAC: A SEGMENT-BASED PARALLEL COMPRESSION FOR BACKUP ACCELERATION IN NONVOLATILE PROCESSORS
Authors:
Xiao Sheng, Yiqun Wang, Yongpan Liu and Huazhong Yang, Tsinghua University, CN
Abstract
16:01IP3-14, 778THE DESIGN OF SUSTAINABLE WIRELESS SENSOR NETWORK NODE USING SOLAR ENERGY AND PHASE CHANGE MEMORY
Authors:
Ping Zhou1, Youtao Zhang2 and Jun Yang2
1Intel, US; 2University of Pittsburgh, US
Abstract
16:02IP3-15, 428OPTICAL LOOK UP TABLE
Authors:
Zhen Li, Sébastien Le Beux, Christelle Monat, Xavier Letartre and Ian O'Connor, Lyon Institute of Nanotechnology, FR
Abstract
16:03IP3-16, 261A VERILOG-A MODEL FOR RECONFIGURABLE LOGIC GATES BASED ON GRAPHENE PN-JUNCTIONS
Authors:
Sandeep Miryrala, Mehrdad Montazeri, Andrea Calimera, Enrico Macii and Massimo Poncino, Politecnico di Torino, IT
Abstract
16:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

7.5 Energy-efficient architectures and software design for power-constrained systems

Date: Wednesday 20 March 2013
Time: 14:30 - 16:00
Location / Room: Meije

Chair:
Geoff Merrett, University of Southampton, UK

Co-Chair:
Gangadhar Garipelli, EPFL, CH

This session proposes new solutions for energy-efficient hardware design and software architectures targetting highly power-constrained environments. The first two papers in this session address energy-optimized architectures and algorithms for distributed systems operating in smart buildings and cars. The last two papers present the design of low-power signal acquisition approaches and innovative processing architectures for electrocorticographic (ECoG) and electrocardiogram (ECG) biosignals analysis.

TimeLabelPresentation Title
Authors
14:307.5.1(Best Paper Award Candidate)
OPTIMAL CONTROL OF A GRID-CONNECTED HYBRID ELECTRICAL ENERGY STORAGE SYSTEM FOR HOMES
Authors:
Yanzhi Wang1, Xue Lin1, Sangyoung Park2, Naehyuck Chang2 and Massoud Pedram1
1University of Southern California, US; 2Seoul National University, KR
Abstract
15:007.5.2RADAR SIGNATURE IN MULTIPLE TARGET TRACKING SYSTEM FOR DRIVER ASSISTANT APPLICATION
Authors:
Haisheng Liu1 and Smail Niar2
1Nantong University, FR; 2Université de Valenciennes, FR
Abstract
15:157.5.3DEVELOPMENT OF A FULLY IMPLANTABLE RECORDING SYSTEM FOR ECOG SIGNALS
Authors:
Jonas Pistor, Janpeter Hoeffmann, David Rotermund, Elena Tolstosheeva, Tim Schellenberg, Dmitriy Boll, Victor Gordillo-Gonzales, Sunita Mandon, Dagmar Peters-Drolshagen, Andreas Kreiter, Martin Schneider, Walter Lang, Klaus Pawelzik and Steffen Paul, University of Bremen, DE
Abstract
15:307.5.4(Best Paper Award Candidate)
A METHODOLOGY FOR EMBEDDED CLASSIFICATION OF HEARTBEATS USING RANDOM PROJECTIONS
Authors:
Rubén Braojos, Giovanni Ansaloni and David Atienza, École Polytechnique Fédérale de Lausanne, CH
Abstract
16:00IP3-17, 279A SURVY OF MULTI-SOURCE ENERGY HARVESTING SYSTEMS
Authors:
Alex S. Weddell1, Michele Magno2, Davide Brunelli3, Geoff V. Merrett1, Bashir M. Al-Hashimi1 and Luca Benini2
1University of Southampton, UK; 2University of Bologna, IT; 3University of Trento, IT
Abstract
16:01IP3-18, 817CAPITAL COST-AWARE DESIGN AND PARTIAL SHADING-AWARE ARCHITECTURE OPTIMIZATION OF A RECONFIGURABLE PHOTOVOLTAIC SYSTEM
Authors:
Yanzhi Wang1, Xue Lin1, Jaemin Kim2, Naehyuck Chang2 and Massoud Pedram1
1University of Southern California, US; 2Seoul National University, KR
Abstract
16:02IP3-19, 863AN ULTRA-LOW POWER HARDWARE ACCELERATOR ARCHITECTURE FOR WEARABLE COMPUTERS USING DYNAMIC TIME WARPING
Authors:
Reza Lotfian and Roozbeh Jafari, University of Texas at Dallas, US
Abstract
16:03IP3-20, 8EFFICIENT CACHE ARCHITECTURES FOR RELIABLE HYBRID VOLTAGE OPERATION USING EDC CODES
Authors:
Bojan Maric1, Jaume Abella2 and Mateo Valero1
1Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES; 2Barcelona Supercomputing Center, ES
Abstract
16:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

7.6 On-Line Approaches Towards Processor Resilience

Date: Wednesday 20 March 2013
Time: 14:30 - 16:00
Location / Room: Bayard

Chair:
Yiorgos Makris, University of Dallas, US

Co-Chair:
Xavier Vera, Intel, ES

This session brings the audience papers dealing with on-line detection and resilience for processors by task replication and redundant execution.

TimeLabelPresentation Title
Authors
14:307.6.1(Best Paper Award Candidate)
EFFICIENT SOFTWARE BASED FAULT TOLERANCE APPROACH ON MULTICORE PLATFORMS
Authors:
Hamid Mushtaq, Zaid Al-Ars and Koen Bertels, TU Delft, NL
Abstract
15:007.6.2USING EXPLICIT OUTPUT COMPARISONS FOR FAULT TOLERANT SCHEDULING (FTS) ON MODERN HIGH-PERFORMANCE PROCESSORS
Authors:
Yue Gao, Sandeep K. Gupta and Melvin Breuer, University of Southern California, US
Abstract
15:307.6.3LOW COST PERMANENT FAULT DETECTION USING ULTRA-REDUCED INSTRUCTION SET CO-PROCESSORS
Authors:
Sundaram Ananthanarayan1, Siddharth Garg2 and Hiren Patel2
1Stanford University, US; 2University of Waterloo, CA
Abstract
16:00IP3-21, 592IMPROVING FAULT TOLERANCE USING HARDWARE-SOFTWARE-CO-SYNTHESIS
Authors:
Heinz Riener1, Stefan Frehse1 and Goerschwin Fey2
1University Bremen, DE; 2German Aerospace Center, DE
Abstract
16:01IP3-22, 444A DYNAMIC SELF-ADAPTIVE CORRECTION METHOD FOR ERROR RESILIENT APPLICATION
Authors:
Luming Yan, Huaguo Liang and Zhengfeng Huang, Hefei University of Technology, CN
Abstract
16:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

7.7 EMBEDDED TUTORIAL: From multi-core SoC to scale-out processors

Date: Wednesday 20 March 2013
Time: 14:30 - 16:00
Location / Room: Les Bans

Organiser:
Marcello Coppola, STMicroelectronics, FR

Chair:
Marcello Coppola, STMicroelectronics, FR

Co-Chair:
Luca Fanucci, University of Pisa, IT

Advanced computing is generally recognized as a way to accelerate progress in scientific research in the 21st Century. Heterogeneous multicore architecture has long been accepted within embedded computing the way to deliver improved performance and subsequent improved power efficiency. However to build a usable system within an affordable power budget both architectures and applications will need to change dramatically. These changes will impact all scales of computing from single MPSoC to racks to supercomputers. The entire computing industry faces the same power, memory, concurrency and programmability challenges. While Mobile, Consumer systems target the best tradeoff between area, performance and power, scale-out datacenters have additional challenges, notably performance per total cost of ownership (performance/TCO). Emerging applications (e.g., data serving and web search) that run in these datacenters operate on vast datasets that are not accommodated by on-die caches of existing server chips. Large caches reduce the die area available for cores and lower performance through long access latency when instructions are fetched. In tutorial, we will introduce the next generation multicore ARM based SoC to address the challenge of maintaining the homogeneity of the software architecture while extending to the benefits of heterogeneity. Then we will introduce the future evolutions of multi-core architectures in mobile and consumer SoCs, describing how gates will be used to meet the new application requirements. Finally, we introduce a methodology for designing scalable and efficient scale-out server processors that facilitates the design of optimal multi-core configurations, which divide the server processor's real estate into performance-optimal modules that couple many lean cores with a small last-level cache to maximize throughput per area given a power budget

TimeLabelPresentation Title
Authors
14:307.7.1THE 64BITS MULTICORE ARM BASED SOC
Author:
John Goodacre, ARM, UK
Abstract
15:007.7.2VIRTICAL: THE VIRTUALIZATION READY SOC PLATFORM FOR MOBILE AND CONSUMER
Authors:
George Kornaros1 and Marcello Coppola2
1TEI, GR; 2STMicroelectronics, FR
Abstract
15:307.7.3SCALE OUT PROCESSORS
Author:
Babak Falsafi, EPFL, CH
Abstract
16:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

UB07 Session 7

Date: Wednesday 20 March 2013
Time: 14:30 - 16:30
Location / Room: Booth 46, Exhibition

TimeLabelPresentation Title
Authors
14:30UB07.1USB STARGATE: AN OPEN-SOURCE HARDWARE DEVICE FOR HUMAN COMPUTER INTERACTION
Authors:
Pablo Viana1, Raiann Dias1 and Lucas Torquato2
1UFAL, BR; 2UFPE, BR
Abstract
14:30UB07.2NOC SYSTEM GENERATOR: NOC SYSTEM GENERATOR - A TOOL FOR FAST PROTOTYPING OF MULTI-CORE SYSTEMS ON FPGAS
Authors:
Johnny Öberg, Francesco Robino, Hosein Attarzadeh and Ingo Sander, KTH Royal Institute of Technology, SE
Abstract
14:30UB07.3HEAP: MULTIPROCESSOR TOOLSET AND ARCHITECTURE
Authors:
Luciano Lavagno1, Mihai Lazarescu1, Ioannis Papaefstathiou2 and Andreas Brokalakis2
1Politecnico di Torino, IT; 2Synelixis, IT
Abstract
14:30UB07.4TCPA: RESOURCE-AWARE VIDEO PROCESSING ON TIGHTLY-COUPLED PROCESSOR ARRAYS
Authors:
Vahid Lari, Srinivas Boppu, Frank Hannig, Shravan Muddassani, Boris Kuzmin and Jürgen Teich, University of Erlangen-Nuremberg, DE
Abstract
14:30UB07.5A RECONFIGURABLE HYPERVISOR FOR MIXED CRITICALITY SYSTEMS
Authors:
Matthias Beckert, Moritz Neukirchner, Tobias Michaels and Rolf Ernst, TU Braunschweig, DE
Abstract
14:30UB07.6LOW-POWER SIGNAL PROCESSING PLATFORM BASED ON NON-UNIFORM SAMPLING AND EVENT-DRIVEN CIRCUITRY
Authors:
Laurent Fesquet1, Tugdual Le pelleter2, Taha Beyrouthy2, Yann Leroy2, Agnès Bonvilain2 and Robin Rolland-Girod3
1TIMA and CIME Nanotech, FR; 2TIMA, FR; 3CIME Nanotech, FR
Abstract
14:30UB07.7CHAMS: A DESIGNER-ASSISTED ANALOG SYNTHESIS FLOW
Authors:
Marie-Minerve Louërat, Jean-Paul Chaput, Ramy Iskander and Stéphanie Youssef, Université Pierre & Marie Curie, FR
Abstract
14:30UB07.8SM2DEA: FROM MATLAB-SIMULINK TO DISTRIBUTED EMBEDDED APPLICATIONS: AN AUTOMOTIVE TOOL DEMONSTRATION
Authors:
Günter Ehmen1, Matthias Büker2, Stefan Henkler2, Achim Rettberg1, Ingo Stierand1 and Eike Thaden2
1Carl von Ossietzky University of Oldenburg, DE; 2OFFIS, DE
Abstract
14:30UB07.9ASAM TOOLS DEMONSTRATION
Authors:
Felipe Chies1, Rosilde Corvino2, Erkan Diken2, Christof Douma3, Agostino Galluzzo4, Deepak Gangadharan5, Roel Jordans2, Lech Jozwiak2, Bart Kienhuis6, Menno Lindwer1, Jan Madsen5, Paolo Meloni7, Laura Micconi5, Giuseppe Notarangelo4, Sebastiano Pomata7, Luigi Raffo7 and Giuseppe Tuveri7
1Intel, NL; 2Eindhoven University of Technology, NL; 3ACE, NL; 4ST, IT; 5DTU, DK; 6Compaan, NL; 7UNICA, IT
Abstract
16:30End of session
19:30DATE Party in World Trade Center, Grenoble, FR

This year the DATE party will take place in the World Trade Center, Grenoble.

The evening will feature a buffet style dinner with plenty of buffet points and drinks to accompany dinner. In an enjoyable atmosphere participants will have the opportunity to meet and mingle with their friends and colleagues. All conference attendees, users, vendors and their guests are encouraged to come to the party. Entrance will be by ticket only, so please check that you receive the party ticket when you register. Additional tickets for the full Evening Social Programme may be obtained for 75 Euros each (see website for booking forms).

There is no transportation and most hotels are located a short tram ride away from the venue

IP3 Interactive Presentations

Date: Wednesday 20 March 2013
Time: 16:00 - 16:30
Location / Room: Exhibition Hall (espace accueil)

Interactive Presentations run simulatenously during a 30-minute slot. A poster associated to the IP paper is on display throughout the afternoon. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session, prior to the actual Interactive Presentation.

LabelPresentation Title
Authors
IP3-1HYPERVISED TRANSIENT SPICE SIMULATIONS OF LARGE NETLISTS & WORKLOADS ON MULTI-PROCESSOR SYSTEMS
Authors:
Grigorios Lyras, Dimitrios Rodopoulos, Antonis Papanikolaou and Dimitrios Soudris, NTUA-ECE-MicroLab, GR
Abstract
IP3-2STATICALLY-SCHEDULED APPLICATION-SPECIFIC PROCESSOR DESIGN: A CASE-STUDY ON MMSE MIMO EQUALIZATION
Authors:
Mostafa Rizk1, Amer Baghdadi2, Michel Jezequel2, Yasser Mohana3 and Youssef Atat3
1Telecom Bretagne, Lebanese University, FR; 2Telecom Bretagne, FR; 3Lebanese University, LB
Abstract
IP3-3EXPLORING RESOURCE MAPPING POLICIES FOR DYNAMIC CLUSTERING ON NOC-BASED MPSOCS
Authors:
Gustavo Girao, Thiago Santini and Flavio Wagner, Federal University of Rio Grande do Sul, BR
Abstract
IP3-4CHARACTERIZING THE PERFORMANCE BENEFITS OF FUSED CPU/GPU SYSTEMS USING FUSIONSIM
Authors:
Vitaly Zakharenko1, Tor Aamodt2 and Andreas Moshovos1
1University of Toronto, CA; 2University of British Columbia, CA
Abstract
IP3-5RELIABILITY ANALYSIS FOR INTEGRATED CIRCUIT AMPLIFIERS USED IN NEURAL MEASUREMENT SYSTEMS
Authors:
Nico Hellwege, Nils Heidmann, Dagmar Peters-Drolshagen and Steffen Paul, University of Bremen, DE
Abstract
IP3-6ON-LINE TESTING OF PERMANENT RADIATION EFFECTS IN RECONFIGURABLE SYSTEMS
Authors:
Luca Cassano1, Dario Cozzi2, Sebastian Korf2, Jens Hagemeyer2, Mario Porrmann2 and Luca Sterpone3
1University of Pisa, IT; 2Bielefeld University, DE; 3Politecnico di Torino, IT
Abstract
IP3-7AN APPROACH FOR REDUNDANCY IN FLEXRAY NETWORKS USING FPGA PARTIAL RECONFIGURATION
Authors:
Shanker Shreejith1, Kizheppatt Vipin1, Suhaib A Fahmy1 and Martin Lukasiewycz2
1Nanyang Technological University, SG; 2TUM CREATE, SG
Abstract
IP3-8FAST CONE-OF-INFLUENCE COMPUTATION AND ESTIMATION IN PROBLEMS WITH MULTIPLE PROPERTIES
Authors:
Carmelo Loiacono1, Marco Palena1, Paolo Pasini1, Denis Patti1, Stefano Quer1, Stefano Ricossa1, Danilo Vendraminetto1 and Jason Baumgartner2
1Politecnico di Torino, IT; 2IBM Research, US
Abstract
IP3-9USING CUBES OF NON-STATE VARIABLES WITH PROPERTY DIRECTED REACHABILITY
Authors:
John Backes and Marc Riedel, University of Minnesota, US
Abstract
IP3-10BRIDGING THE GAP BETWEEN DUAL PROPAGATION AND CNF-BASED QBF SOLVING
Authors:
Alexandra Goultiaeva1, Martina Seidl2 and Armin Biere2
1University of Toronto, CA; 2Johannes Kepler University, AT
Abstract
IP3-11DANCE: DISTRIBUTED APPLICATION-AWARE NODE CONFIGURATION ENGINE IN SHARED RECONFIGURABLE SENSOR NETWORKS
Authors:
Chih-Ming Hsieh, Zhonglei Wang and Jörg Henkel, Karlsruhe Institute of Technology, DE
Abstract
IP3-12HYBRID INTERCONNECT DESIGN FOR HETEROGENEOUS HARDWARE ACCELERATORS
Authors:
Cuong Pham-Quoc1, Jan Heisswolf2, Stephan Werner2, Zaid Al-Ars1, Jürgen Becker2 and Koen Bertels1
1Delft University of Technology, NL; 2Karlsruhe Institute of Technology, DE
Abstract
IP3-13SPAC: A SEGMENT-BASED PARALLEL COMPRESSION FOR BACKUP ACCELERATION IN NONVOLATILE PROCESSORS
Authors:
Xiao Sheng, Yiqun Wang, Yongpan Liu and Huazhong Yang, Tsinghua University, CN
Abstract
IP3-14THE DESIGN OF SUSTAINABLE WIRELESS SENSOR NETWORK NODE USING SOLAR ENERGY AND PHASE CHANGE MEMORY
Authors:
Ping Zhou1, Youtao Zhang2 and Jun Yang2
1Intel, US; 2University of Pittsburgh, US
Abstract
IP3-15OPTICAL LOOK UP TABLE
Authors:
Zhen Li, Sébastien Le Beux, Christelle Monat, Xavier Letartre and Ian O'Connor, Lyon Institute of Nanotechnology, FR
Abstract
IP3-16A VERILOG-A MODEL FOR RECONFIGURABLE LOGIC GATES BASED ON GRAPHENE PN-JUNCTIONS
Authors:
Sandeep Miryrala, Mehrdad Montazeri, Andrea Calimera, Enrico Macii and Massimo Poncino, Politecnico di Torino, IT
Abstract
IP3-17A SURVY OF MULTI-SOURCE ENERGY HARVESTING SYSTEMS
Authors:
Alex S. Weddell1, Michele Magno2, Davide Brunelli3, Geoff V. Merrett1, Bashir M. Al-Hashimi1 and Luca Benini2
1University of Southampton, UK; 2University of Bologna, IT; 3University of Trento, IT
Abstract
IP3-18CAPITAL COST-AWARE DESIGN AND PARTIAL SHADING-AWARE ARCHITECTURE OPTIMIZATION OF A RECONFIGURABLE PHOTOVOLTAIC SYSTEM
Authors:
Yanzhi Wang1, Xue Lin1, Jaemin Kim2, Naehyuck Chang2 and Massoud Pedram1
1University of Southern California, US; 2Seoul National University, KR
Abstract
IP3-19AN ULTRA-LOW POWER HARDWARE ACCELERATOR ARCHITECTURE FOR WEARABLE COMPUTERS USING DYNAMIC TIME WARPING
Authors:
Reza Lotfian and Roozbeh Jafari, University of Texas at Dallas, US
Abstract
IP3-20EFFICIENT CACHE ARCHITECTURES FOR RELIABLE HYBRID VOLTAGE OPERATION USING EDC CODES
Authors:
Bojan Maric1, Jaume Abella2 and Mateo Valero1
1Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES; 2Barcelona Supercomputing Center, ES
Abstract
IP3-21IMPROVING FAULT TOLERANCE USING HARDWARE-SOFTWARE-CO-SYNTHESIS
Authors:
Heinz Riener1, Stefan Frehse1 and Goerschwin Fey2
1University Bremen, DE; 2German Aerospace Center, DE
Abstract
IP3-22A DYNAMIC SELF-ADAPTIVE CORRECTION METHOD FOR ERROR RESILIENT APPLICATION
Authors:
Luming Yan, Huaguo Liang and Zhengfeng Huang, Hefei University of Technology, CN
Abstract

UB08 Session 8

Date: Wednesday 20 March 2013
Time: 16:30 - 18:30
Location / Room: Booth 46, Exhibition

TimeLabelPresentation Title
Authors
16:30UB08.1AUDIO SIGNAL RECONSTRUCTION FROM A DAMAGED COCHLEA MODEL
Authors:
Umberto Cerasani1 and William Tatinian2
1LEAT, FR; 2UNICE, FR
Abstract
16:30UB08.2EDA TOOLS FOR DEPENDABLE SYSTEM DESIGN METHODOLOGY
Authors:
Ken Yano, Mitsugu Ogawa, Ryota Yoshinaga, Takahito Yoshiki, Takanori Hayashida and Toshinori Sato, Fukuoka University, JP
Abstract
16:30UB08.3HEAP: MULTIPROCESSOR TOOLSET AND ARCHITECTURE
Authors:
Luciano Lavagno1, Mihai Lazarescu1, Ioannis Papaefstathiou2 and Andreas Brokalakis2
1Politecnico di Torino, IT; 2Synelixis, IT
Abstract
16:30UB08.4TACP: TEST AND CHARACTERIZATION PLATFORM
Authors:
Muhammad Elrabaa and Amran Al-Aghbari, King Fahd University of Petroleum and Minerals, SA
Abstract
16:30UB08.5EMBEDDED GREEN SYSTEM PROJECT: POWER MANAGEMENT TECHNIQUES FOR THE HARVESTED ENERGY BASED SYSTEM
Authors:
Kyungsoo Lee and Tohru Ishihara, Kyoto University, JP
Abstract
16:30UB08.6FASTCUDA: OPEN SOURCE FPGA ACCELERATOR & HARDWARE-SOFTWARE CODESIGN TOOLSET FOR CUDA KERNELS
Authors:
Iakovos Mavroidis1, Luciano Lavagno2, Ioannis Mavroidis1, Ioannis Papaefstathiou1, Mihai Lazarescu2, Andrés Otero3, Eduardo de la Torre3 and Florian Schäfer4
1Microprocessor and Hardware Lab, Technical University of Crete, GR; 2Politecnico di Torino, IT; 3Universidad Politécnica de Madrid, ES; 4FSResult GmbH, DE
Abstract
16:30UB08.7VUART: DEBUG OF A DESIGN EMBEDDING 24 MICRO-BLAZES ON A ZYNQ
Authors:
Pierre Bomel, Jean-Philippe Diguet and Kevin Martin, Université de Bretagne Sud, FR
Abstract
16:30UB08.8DATAFLOW-BASED ADAPTIVE MULTICORE EXECUTION ON A XILINX ZYNQ PLATFORM
Authors:
Julien Heulot, Yaset Oliva, Maxime Pelcat, Jean-François Nezan and Jean-Christophe Prevotet, INSA Rennes, IETR, FR
Abstract
16:30UB08.9BUILT-IN P/N SELF-ADJUSTMENT: POST-SILICON P/N-PERFORMANCE COMPENSATION SCHEME COMPATIBLE WITH CELL-BASED DESIGN
Authors:
A.K.M. Mahfuzul Islam, Norihiro Kamae, Tohru Ishihara and Hidetoshi Onodera, Kyoto University, JP
Abstract
18:30End of session
19:30DATE Party in World Trade Center, Grenoble, FR

This year the DATE party will take place in the World Trade Center, Grenoble.

The evening will feature a buffet style dinner with plenty of buffet points and drinks to accompany dinner. In an enjoyable atmosphere participants will have the opportunity to meet and mingle with their friends and colleagues. All conference attendees, users, vendors and their guests are encouraged to come to the party. Entrance will be by ticket only, so please check that you receive the party ticket when you register. Additional tickets for the full Evening Social Programme may be obtained for 75 Euros each (see website for booking forms).

There is no transportation and most hotels are located a short tram ride away from the venue

8.1 SPECIAL DAY on "High-Performance Low-Power Computing" HOT TOPIC - Fabrication Technology Approaches to Energy-Efficiency

Date: Wednesday 20 March 2013
Time: 17:00 - 18:30
Location / Room: Oisans

Organiser:
Ahmed Jerraya, CEA-LETI-MINATEC, FR

Chair:
Ahmed Jerraya, CEA-LETI-MINATEC, FR

Co-Chair:
Ahmed Jerraya, CEA-LETI-MINATEC, FR

SoC designs integrate an increasing number of heterogeneous programmable units (CPU, GPU, ASIP sub-systems), sophisticated interconnect, innovative memory architecture, and are using energy-efficient libraries that target advanced fabrication process technologies. This Hot-Topic Session presents the key challenges for aligning the most advanced fabrication technologies, FDSOI with circuit and architecture technologies to master energy-efficiency.

TimeLabelPresentation Title
Authors
17:008.1.1UTBB FD-SOI: A PROCESS/DESIGN SYMBIOSIS FOR BREAKTHROUGH ENERGY-EFFICIENCY
Authors:
Philippe Magarshack, Philippe Flatresse and Giorgio Cesana, STMicroelectronics, FR
Abstract
17:208.1.2WIRELESS INTERCONNECT FOR BOARD AND CHIP LEVEL
Authors:
Gerhard Fettweis, Najeeb ul Hassan, Lukas Landau and Erik Fischer, TU Dresden, DE
Abstract
17:408.1.3ENERGY-EFFICIENT LIBRARIES
Author:
Yannick Nevers, ARM, FR
Abstract
18:008.1.4FUTURE MEMORY AND INTERCONNECT TECHNOLOGIES
Author:
Yuan Xie, Pennsylvania State University, US
Abstract
18:30End of session
19:30DATE Party in World Trade Center, Grenoble, FR

This year the DATE party will take place in the World Trade Center, Grenoble.

The evening will feature a buffet style dinner with plenty of buffet points and drinks to accompany dinner. In an enjoyable atmosphere participants will have the opportunity to meet and mingle with their friends and colleagues. All conference attendees, users, vendors and their guests are encouraged to come to the party. Entrance will be by ticket only, so please check that you receive the party ticket when you register. Additional tickets for the full Evening Social Programme may be obtained for 75 Euros each (see website for booking forms).

There is no transportation and most hotels are located a short tram ride away from the venue

8.2 Scheduling for Real-Time Embedded Systems

Date: Wednesday 20 March 2013
Time: 17:00 - 18:30
Location / Room: Belle-Etoile

Chair:
Wido Kruijtzer, Synopsys, NL

Co-Chair:
Jan Madsen, Technical University of Denmark, DK

The first paper addresses the challenge of integrating a safety-critical real-time system consisting of a set of single cores into a multi-core system, with the aim to reduce recertification cost. The second paper presents a scheduling approach for multiple media streams, efficiently utilizing available resources. The third paper presents a methodology for the priority assignment of processes and messages in event-triggered systems with tight end-to-end real-time deadlines.

TimeLabelPresentation Title
Authors
17:008.2.1OPTIMIZED SCHEDULING OF MULTI-IMA PARTITIONS WITH EXCLUSIVE REGION FOR SYNCHRONIZED REAL-TIME MULTI-CORE SYSTEMS
Authors:
Jung-Eun Kim1, Man-Ki Yoon1, Sungjin Im2, Richard Bradford3 and Lui Sha1
1University of Illinois at Urbana-Champaign, US; 2Department of Computer Science, Duke University, US; 3Rockwell Collins, US
Abstract
17:308.2.2QUALITY-AWARE MEDIA SCHEDULING ON MPSOC PLATFORMS
Authors:
Deepak Gangadharan1, Samarjit Chakraborty2 and Roger Zimmermann3
1DTU Informatics, DK; 2Technische Universität München, DE; 3National University of Singapore, SG
Abstract
18:008.2.3PRIORITY ASSIGNMENT FOR EVENT-TRIGGERED SYSTEMS USING MATHEMATICAL PROGRAMMING
Authors:
Martin Lukasiewycz1, Sebastian Steinhorst1 and Samarjit Chakraborty2
1TUM CREATE, SG; 2Technische Universität München, DE
Abstract
18:30IP4-1, 931EFFICIENT AND SCALABLE OPENMP-BASED SYSTEM-LEVEL DESIGN
Authors:
Alessandro Cilardo, Luca Gallo, Antonino Mazzeo and Nicola Mazzocca, University of Naples Federico II, IT
Abstract
18:31IP4-2, 601UTILIZING VOLTAGE-FREQUENCY ISLANDS IN C-TO-RTL SYNTHESIS FOR STREAMING APPLICATIONS
Authors:
Xinyu He1, Shuangchen Li1, Yongpan Liu1, X. Sharon Hu2 and Huazhong Yang1
1Tsinghua University, CN; 2University of Notre Dame, US
Abstract
18:30End of session
19:30DATE Party in World Trade Center, Grenoble, FR

This year the DATE party will take place in the World Trade Center, Grenoble.

The evening will feature a buffet style dinner with plenty of buffet points and drinks to accompany dinner. In an enjoyable atmosphere participants will have the opportunity to meet and mingle with their friends and colleagues. All conference attendees, users, vendors and their guests are encouraged to come to the party. Entrance will be by ticket only, so please check that you receive the party ticket when you register. Additional tickets for the full Evening Social Programme may be obtained for 75 Euros each (see website for booking forms).

There is no transportation and most hotels are located a short tram ride away from the venue

8.3 Logic Synthesis Techniques

Date: Wednesday 20 March 2013
Time: 17:00 - 18:30
Location / Room: Stendahl

Chair:
Michel Berkelaar, Delft University of Technology, NL

Co-Chair:
Jordi Cortadella, Universitat Politècnica Catalunya, ES

The first paper of this session presents a new multi-level optimization technique based on Boolean Relations. The second paper proposes a methodology to incorporate human intuition into Engineering Change Orders. The third paper describes a retiming technique for Soft-Error optimization.

TimeLabelPresentation Title
Authors
17:008.3.1(Best Paper Award Candidate)
MINIMIZATION OF P-CIRCUITS USING BOOLEAN RELATIONS
Authors:
Anna Bernasconi1, Valentina Ciriani2, Gabriella Trucco2 and Tiziano Villa3
1University of Pisa, IT; 2Università degli Studi di Milano, IT; 3Universita' degli Studi di Verona, IT
Abstract
17:308.3.2INTUITIVE ECO SYNTHESIS FOR HIGH PERFORMANCE CIRCUITS
Authors:
Haoxing Ren1, Ruchir Puri1, Lakshmi Reddy1, Smita Krishnaswamy2, Cindy Washburn1, Joel Earl1 and Joachim Keinert3
1IBM, US; 2Columbia University, US; 3IBM, DE
Abstract
18:008.3.3RETIMING FOR SOFT ERROR MINIMIZATION UNDER ERROR-LATCHING WINDOW CONSTRAINTS
Authors:
Yinghai Lu1 and Hai Zhou2
1Synopsys, US; 2Northwestern University, US
Abstract
18:30IP4-3, 21BICONDITIONAL BDD: A NOVEL CANONICAL BDD FOR LOGIC SYNTHESIS TARGETING XOR-RICH CIRCUITS
Authors:
Luca Amarú, Pierre-Emmanuel Gaillardon and Giovanni De Micheli, EPFL, CH
Abstract
18:31IP4-4, 550OPTIMIZING BDDS FOR TIME-SERIES DATASET MANIPULATION
Authors:
Stergios Stergiou and Jawahar Jain, Fujitsu, US
Abstract
18:32IP4-5, 633INCORPORATING THE IMPACTS OF WORKLOAD-DEPENDENT RUNTIME VARIATIONS INTO TIMING ANALYSIS
Authors:
Farshad Firouzi1, Saman Kiamehr1, Sani Nassif2 and Mehdi Tahoori1
1Karlsruhe Institute of Technology, DE; 2IBM, US
Abstract
18:30End of session
19:30DATE Party in World Trade Center, Grenoble, FR

This year the DATE party will take place in the World Trade Center, Grenoble.

The evening will feature a buffet style dinner with plenty of buffet points and drinks to accompany dinner. In an enjoyable atmosphere participants will have the opportunity to meet and mingle with their friends and colleagues. All conference attendees, users, vendors and their guests are encouraged to come to the party. Entrance will be by ticket only, so please check that you receive the party ticket when you register. Additional tickets for the full Evening Social Programme may be obtained for 75 Euros each (see website for booking forms).

There is no transportation and most hotels are located a short tram ride away from the venue

8.4 High-Speed Robust NoCs

Date: Wednesday 20 March 2013
Time: 17:00 - 18:30
Location / Room: Chartreuse

Chair:
Luca Carloni, Columbia University, US

Co-Chair:
Frédéric Pétrot, TIMA, FR

This session explores the challenges and opportunities offered by current and future manufacturing technologies. The first paper proposes a cutting-edge, extremely-high-frequency implementation. The other two papers take steps to combat aging effects due to NBTI phenomena.

TimeLabelPresentation Title
Authors
17:008.4.1EXPLORING TOPOLOGIES FOR A SOURCE-SYNCHRONOUS RING-BASED NETWORK-ON-CHIP
Speaker:
Jacob Abraham, University of Texas at Austin, US
Authors:
Ayan Mandal, Sunil Khatri and Rabi Mahapatra, Texas A&M University, US
Abstract
17:308.4.2PROACTIVE AGING MANAGEMENT IN HETEROGENEOUS NOCS THROUGH A CRITICALITY-DRIVEN ROUTING APPROACH
Authors:
Dean Michael Ancajas, Koushik Chakraborty and Sanghamitra Roy, Utah State University, US
Abstract
18:008.4.3SENSOR-WISE METHODOLOGY TO FACE NBTI STRESS OF NOC BUFFERS
Authors:
Davide Zoni and William Fornaciari, Politecnico di Milano, IT
Abstract
18:30IP4-6, 147AN AREA-EFFICIENT NETWORK INTERFACE FOR A TDM-BASED NETWORK-ON-CHIP
Authors:
Jens Sparsø, Evangelia Kasapaki and Martin Schoeberl, Technical University of Denmark, DK
Abstract
18:31IP4-7, 542CARS: CONGESTION-AWARE REQUEST SCHEDULER FOR NETWORK INTERFACES IN NOC-BASED MANYCORE SYSTEMS
Authors:
Masoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila and Hannu Tenhunen, University of Turku, FI
Abstract
18:30End of session
19:30DATE Party in World Trade Center, Grenoble, FR

This year the DATE party will take place in the World Trade Center, Grenoble.

The evening will feature a buffet style dinner with plenty of buffet points and drinks to accompany dinner. In an enjoyable atmosphere participants will have the opportunity to meet and mingle with their friends and colleagues. All conference attendees, users, vendors and their guests are encouraged to come to the party. Entrance will be by ticket only, so please check that you receive the party ticket when you register. Additional tickets for the full Evening Social Programme may be obtained for 75 Euros each (see website for booking forms).

There is no transportation and most hotels are located a short tram ride away from the venue

8.5 Industrial Experiences with Embedded System Design

Date: Wednesday 20 March 2013
Time: 17:00 - 18:30
Location / Room: Meije

Chair:
Roberto Zafalon, ST Microelectronics, IT

Co-Chair:
Ralf Pferdmenges, Infineon Technologies, DE

This session feature six industrial research and practice cases for the design of embedded systems. Attendees will learn about future research demands and latest developments in design automation and embedded software.

TimeLabelPresentation Title
Authors
17:008.5.1(Best Paper Award Candidate)
DESIGNING TIGHTLY-COUPLED EXTENSION UNITS FOR THE STXP70 PROCESSOR
Authors:
Yves Janin, Valérie Bertin, Hervé Chauvet, Thomas Deruyter, Christophe Eichwald, Olivier-André Giraud, Vincent Lorquet and Thomas Thery, STMicroelectronics, FR
Abstract
17:158.5.2FAST AND ACCURATE METHODOLOGY FOR POWER ESTIMATION AND REDUCTION OF PROGRAMMABLE ARCHITECTURE
Authors:
Erwan Piriou1, Raphael David1, Fahim Rahim2 and Solaiman Rahim3
1CEA LIST, FR; 2Atrenta, FR; 3Atrenta, US
Abstract
17:308.5.3A GATE LEVEL METHODOLOGY FOR EFFICIENT STATISTICAL LEAKAGE ESTIMATION IN COMPLEX 32NM CIRCUITS
Authors:
Smriti Joshi1, Anne Lombardot1, Marc Belleville2, Edith Beigne2 and Stephane Girard3
1STMicroelectronics, FR; 2CEA, FR; 3INRIA, FR
Abstract
17:458.5.4A NEAR-FUTURE PREDICTION METHOD FOR LOW POWER CONSUMPTION ON A MANY-CORE PROCESSOR
Authors:
Takeshi Kodaka, Akira Takeda, Shunsuke Sasaki, Akira Yokosawa, Toshiki Kizu, Takahiro Tokuyoshi, Hui Xu, Toru Sano, Hiroyuki Usui, Jun Tanabe, Takashi Miyamori and Nobu Matsumoto, Toshiba, JP
Abstract
18:008.5.5TIME- AND ANGLE-TRIGGERED REAL-TIME KERNEL FOR POWERTRAIN APPLICATIONS
Authors:
Damien Chabrol1, Didier Roux1, Vincent David2, Mathieu Jan2, Moha Ait Hmid2, Gilles Zeppa3 and Patrice Oudin3
1Krono-Safe, FR; 2CEA LIST, FR; 3Delphi Diesel Systems, FR
Abstract
18:158.5.6AN EXTREMELY COMPACT JPEG ENCODER FOR ADAPTIVE EMBEDDED SYSTEMS
Authors:
Josef Schneider and Sri Parameswaran, UNSW, AU
Abstract
18:30End of session
19:30DATE Party in World Trade Center, Grenoble, FR

This year the DATE party will take place in the World Trade Center, Grenoble.

The evening will feature a buffet style dinner with plenty of buffet points and drinks to accompany dinner. In an enjoyable atmosphere participants will have the opportunity to meet and mingle with their friends and colleagues. All conference attendees, users, vendors and their guests are encouraged to come to the party. Entrance will be by ticket only, so please check that you receive the party ticket when you register. Additional tickets for the full Evening Social Programme may be obtained for 75 Euros each (see website for booking forms).

There is no transportation and most hotels are located a short tram ride away from the venue

8.6 DfT Methods

Date: Wednesday 20 March 2013
Time: 17:00 - 18:30
Location / Room: Bayard

Chair:
Peter Harrod, ARM, UK

Co-Chair:
Luigi Dillilo, LIRMM, FR

This session deals with DfT for new design techniques and strategies seen in today's IC manufacturing. Furthermore, algorithmic optimizations to improve test and diagnosis are presented.

TimeLabelPresentation Title
Authors
17:008.6.1(Best Paper Award Candidate)
NON-INVASIVE PRE-BOND TSV TEST USING RING OSCILLATORS AND MULTIPLE VOLTAGE LEVELS
Authors:
Sergej Deutsch and Krishnendu Chakrabarty, Duke University, US
Abstract
17:308.6.2LFSR SEED COMPUTATION AND REDUCTION USING SMT-BASED FAULT-CHAINING
Authors:
Dhrumeel Bakshi and Michael Hsiao, Virginia Tech, US
Abstract
18:008.6.3SCAN DESIGN WITH SHADOW FLIP-FLOPS FOR LOW PERFORMANCE OVERHEAD AND CONCURRENT DELAY FAULT DETECTION
Authors:
Sébastien Sarrazin1, Samuel Evain1, Lirida Alves de Barros Naviner2, Yannick Bonhomme1 and Valentin Gherman1
1CEA, LIST, FR; 2Telecom ParisTech, FR
Abstract
18:158.6.4ON CANDIDATE FAULT SETS FOR FAULT DIAGNOSIS AND DOMINANCE GRAPHS OF EQUIVALENCE CLASSES
Author:
Irith Pomeranz, Purdue University, US
Abstract
18:30IP4-8, 854A FAST AND EFFICIENT DFT FOR TEST AND DIAGNOSIS OF POWER SWITCHES IN SOCS
Authors:
Xiaoyu Huang, Jimson Mathew, Rishad A Shafik, Subhashish Bhattacharjee and Dhiraj K Pradhan, University of Bristol, UK
Abstract
18:30End of session
19:30DATE Party in World Trade Center, Grenoble, FR

This year the DATE party will take place in the World Trade Center, Grenoble.

The evening will feature a buffet style dinner with plenty of buffet points and drinks to accompany dinner. In an enjoyable atmosphere participants will have the opportunity to meet and mingle with their friends and colleagues. All conference attendees, users, vendors and their guests are encouraged to come to the party. Entrance will be by ticket only, so please check that you receive the party ticket when you register. Additional tickets for the full Evening Social Programme may be obtained for 75 Euros each (see website for booking forms).

There is no transportation and most hotels are located a short tram ride away from the venue

8.7 Monitoring and Control of Cyber Physical Systems

Date: Wednesday 20 March 2013
Time: 17:00 - 18:30
Location / Room: Les Bans

Chair:
Rolf Ernst, Technische Universität Braunschweig, DE

Co-Chair:
Haibo Zeng, McGill University, CA

Cyber-physical systems deal with the tight integration of computers and physical processes, with control and communication as enabling technologies. The integrative aspect is present in all papers, of which the third one focuses on communications, the fourth and fifth ones on controls, and the first two on a combination thereof.

TimeLabelPresentation Title
Authors
17:008.7.1(Best Paper Award Candidate)
CONTROL-QUALITY DRIVEN DESIGN OF CYBER-PHYSICAL SYSTEMS WITH ROBUSTNESS GUARANTEES
Authors:
Amir Aminifar1, Petru Eles1, Zebo Peng1 and Anton Cervin2
1Linköping University, SE; 2Lund University, SE
Abstract
17:308.7.2COMPOSITIONAL ANALYSIS OF SWITCHED ETHERNET TOPOLOGIES
Authors:
Reinhard Schneider, Licong Zhang, Dip Goswami, Alejandro Masrur and Samarjit Chakraborty, Technische Universität München, DE
Abstract
17:458.7.3SUPERVISOR SYNTHESIS FOR CONTROLLER UPGRADES
Authors:
Johannes Kloos and Rupak Majumdar, MPI-SWS, DE
Abstract
18:008.7.4EVENT DENSITY ANALYSIS FOR EVENT TRIGGERED CONTROL SYSTEMS
Authors:
Tobias Bund, Benjamin Menhorn and Frank Slomka, Ulm University, DE
Abstract
18:158.7.5MODEL PREDICTIVE CONTROL OVER DELAY-BASED DIFFERENTIATED SERVICES CONTROL NETWORKS
Authors:
Riccardo Muradore, Davide Quaglia and Paolo Fiorini, University of Verona, IT
Abstract
18:30IP4-9, 227MULTIRATE CONTROLLER DESIGN FOR RESOURCE- AND SCHEDULE-CONSTRAINED AUTOMOTIVE ECUS
Authors:
Dip Goswami1, Alejandro Masrur1, Reinhard Schneider1, Chun Jason Xue2 and Samarjit Chakraborty1
1Technische Universität München, DE; 2City University of Hong Kong, HK
Abstract
18:31IP4-10, 402DESIGN OF AN ULTRA-LOW POWER DEVICE FOR AIRCRAFT STRUCTURAL HEALTH MONITORING
Authors:
Alessandro Perelli1, Carlo Caione1, Luca De Marchi1, Davide Brunelli2, Alessandro Marzani1 and Luca Benini1
1University of Bologna, IT; 2University of Trento, IT
Abstract
18:30End of session
19:30DATE Party in World Trade Center, Grenoble, FR

This year the DATE party will take place in the World Trade Center, Grenoble.

The evening will feature a buffet style dinner with plenty of buffet points and drinks to accompany dinner. In an enjoyable atmosphere participants will have the opportunity to meet and mingle with their friends and colleagues. All conference attendees, users, vendors and their guests are encouraged to come to the party. Entrance will be by ticket only, so please check that you receive the party ticket when you register. Additional tickets for the full Evening Social Programme may be obtained for 75 Euros each (see website for booking forms).

There is no transportation and most hotels are located a short tram ride away from the venue

8.8 HOT TOPIC: Countering Counterfeit Attacks on Micro-Electronics

Date: Wednesday 20 March 2013
Time: 17:00 - 18:30
Location / Room: Lesdigiueres (Exhibition Theatre)

Organisers:
Ingrid Verbauwhede, KU Leuven, BE
Erik Jan Marinissen, IMEC, BE

Chair:
Steven Jeter, Infineon Technologies, DE

Co-Chair:
Ingrid Verbauwhede, KU Leuven, BE

Counterfeited ICs are an increasing problem. In 2011, a record high of 1,363 counterfeit-part incidents were reported world-wide, representing a $169B risk. Counterfeit incidents include the relatively straight-forward extra production at an outsourced manufacturing site for sales through alternative channels, but also the technically more advanced Trojan Horse "sniffer" ICs hidden in a 3D die stack of a telecom product. What can semiconductor suppliers do in technology, design, and test to assure that their customers get to use only genuine components in their systems?

TimeLabelPresentation Title
Authors
17:008.8.1ANTI-COUNTERFEITING TECHNOLOGIES IMPLEMENTATION INTO IC PACKAGES: CHALLENGES AND ACHIEVEMENTS
Authors:
Nathalie Kae-Nune and Stephanie Pesseguier, STMicroelectronics, FR
Abstract
17:308.8.2ANTI-COUNTERFEITING TECHNIQUES IN IC DESIGN
Author:
Benjamin Levine, Cryptography Research, US
Abstract
18:008.8.3ANTI-COUNTERFEITING WITH HARDWARE INTRINSIC SECURITY
Authors:
Vincent van der Leest and Pim Tuyls, Intrinsic-ID, NL
Abstract
18:30End of session
19:30DATE Party in World Trade Center, Grenoble, FR

This year the DATE party will take place in the World Trade Center, Grenoble.

The evening will feature a buffet style dinner with plenty of buffet points and drinks to accompany dinner. In an enjoyable atmosphere participants will have the opportunity to meet and mingle with their friends and colleagues. All conference attendees, users, vendors and their guests are encouraged to come to the party. Entrance will be by ticket only, so please check that you receive the party ticket when you register. Additional tickets for the full Evening Social Programme may be obtained for 75 Euros each (see website for booking forms).

There is no transportation and most hotels are located a short tram ride away from the venue

Party DATE Party

Date: Wednesday 20 March 2013
Time: 19:30 - 23:00
Location / Room: World Trade Center, Grenoble, FR

This year the DATE party will take place in the World Trade Center, Grenoble.

The evening will feature a buffet style dinner with plenty of buffet points and drinks to accompany dinner. In an enjoyable atmosphere participants will have the opportunity to meet and mingle with their friends and colleagues. All conference attendees, users, vendors and their guests are encouraged to come to the party. Entrance will be by ticket only, so please check that you receive the party ticket when you register. Additional tickets for the full Evening Social Programme may be obtained for 75 Euros each (see website for booking forms).

There is no transportation and most hotels are located a short tram ride away from the venue

TimeLabelPresentation Title
Authors
23:00End of session

9.1 SPECIAL DAY on "Electronic Technologies for Smart Cities" - HOT TOPIC: Smart Grid and Buildings

Date: Thursday 21 March 2013
Time: 08:30 - 10:00
Location / Room: Oisans

Organiser:
Luca Benini, Università di Bologna, IT

Chair:
Andrea Acquaviva, Politecnico di Torino, IT

Co-Chair:
Luca Benini, Università di Bologna, IT

This session will provide a top-down view of energy management and optimization in Smart Environments, with emphasis on Buildings and grid-level integration. The first paper will focus on the design and computer-aided optimization of regional policies for generation, storage and distribution of sustainable energy. The second paper will give a holistic view of grids and building as cyber-physical systems and propose autonomic approaches for managing them. Finally, the third paper will look at design challenges for the distributed smart energy metering infrastructure, with the ultimate goal of reaching self-sustainability through energy harvesting

TimeLabelPresentation Title
Authors
08:309.1.1SUSTAINABLE ENERGY POLICIES: RESEARCH CHALLENGES AND OPPORTUNITIES
Author:
Michela Milano, University of Bologna, IT
Abstract
09:309.1.2SELF-AWARE CYBER-PHYSICAL SYSTEMS AND APPLICATIONS IN SMART BUILDINGS AND CITIES
Authors:
Levent Gurgen, Ozan Gunalp, Yazid Benazzouz and Mathieu Galissot, CEA-Leti, FR
Abstract
10:009.1.3PERPETUAL AND LOW-COST POWER METER FOR MONITORING RESIDENTIAL AND INDUSTRIAL APPLIANCES
Authors:
Davide Brunelli1, Giacomo Paci2, Domenico Balsamo3 and Danilo Porcarelli3
1University of Trento, IT; 2Wispes, IT; 3University of Bologna, IT
Abstract
10:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

9.2 System-Level Analysis and Simulation

Date: Thursday 21 March 2013
Time: 08:30 - 10:00
Location / Room: Belle-Etoile

Chair:
Wolfgang Müller, University of Paderborn, DE

Co-Chair:
Christian Haubelt, University of Rostock, DE

This session covers different approaches to system-level analysis and simulation. The first two papers propose novel techniques to improve accuracy and simulation speed for TLM and dataflow models. The last two papers present novel approaches to timing analysis and model understanding.

TimeLabelPresentation Title
Authors
08:309.2.1(Best Paper Award Candidate)
ANALYTICAL TIMING ESTIMATION FOR TEMPORALLY DECOUPLED TLMS CONSIDERING RESOURCE CONFLICTS
Authors:
Kun Lu, Daniel Mueller-Gritschneder and Ulf Schlichtmann, Technische Universität München, DE
Abstract
09:009.2.2TOWARDS PERFORMANCE ANALYSIS OF SDFGS MAPPED TO SHARED-BUS ARCHITECTURES USING MODEL-CHECKING
Authors:
Maher Fakih1, Kim Grüttner1, Martin Fränzle2 and Achim Rettberg2
1OFFIS, DE; 2Carl von Ossietzky University of Oldenburg, DE
Abstract
09:309.2.3TOWARD POLYCHRONOUS ANALYSIS AND VALIDATION FOR TIMED SOFTWARE ARCHITECTURES IN AADL
Authors:
Yue Ma1, Huafeng Yu1, Thierry Gautier1, Loic Besnard2, Paul Le Guernic1, Jean-Pierre Talpin1 and Maurice Heitz3
1INRIA, FR; 2IRISA/CNRS, FR; 3C-S Communication & Systems, FR
Abstract
09:459.2.4TUNING DYNAMIC DATA FLOW ANALYSIS TO SUPPORT DESIGN UNDERSTANDING
Authors:
Jan Malburg1, Alexander Finder1 and Görschwin Fey2
1University of Bremen, DE; 2German Aerospace Center, DE
Abstract
10:00IP4-11, 318(Best Paper Award Candidate)
FAST AND ACCURATE TLM SIMULATIONS USING TEMPORAL DECOUPLING FOR FIFO-BASED COMMUNICATIONS
Authors:
Claude Helmstetter1, Jérôme Cornet2, Matthieu Moy3, Pascal Vivet1 and Bruno Galilée2
1CEA-Leti, FR; 2STMicroelectronics, FR; 3Verimag, FR
Abstract
10:01IP4-12, 662DETERMINING RELEVANT MODEL ELEMENTS FOR THE VERIFICATION OF UML/OCL SPECIFICATIONS
Authors:
Julia Seiter, Robert Wille, Mathias Soeken and Rolf Drechsler, University of Bremen, DE
Abstract
10:02IP4-13, 667TOWARDS A GENERIC VERIFICATION METHODOLOGY FOR SYSTEM MODELS
Authors:
Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann and Rolf Drechsler, University of Bremen, DE
Abstract
10:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

9.3 Thermal/Power Management Techniques for Energy-Efficient Systems

Date: Thursday 21 March 2013
Time: 08:30 - 10:00
Location / Room: Stendahl

Chair:
Wolfgang Nebel, University of Oldenburg, DE

Co-Chair:
Alberto Macii, Politecnico di Torino, IT

This session presents four papers on power/thermal techniques for energy efficient systems. The first paper proposes an ultra-low-power management circuit for a miniature sensor node completely powered by an energy harvester for autonomous operation. The second paper presents a bio-inspired power saving method to reduce the power consumption of LED backlit panels. The third paper combines clock and power gating to save energy in disabled flip-fops. And finally the fourth paper introduces a new thermal sensor placement algorithm by exploiting the correlation of power estimation errors among functional blocks.

TimeLabelPresentation Title
Authors
08:309.3.1(Best Paper Award Candidate)
A SUB-UA POWER MANAGEMENT CIRCUIT IN 0.18UM CMOS FOR ENERGY HARVESTERS
Authors:
Biswajit Mishra, Cyril Botteron, Gabriele Tasselli, Christian Robert and Pierre A Farine, EPFL, CH
Abstract
09:009.3.2SALIENCY AWARE DISPLAY POWER MANAGEMENT
Authors:
Yang Xiao1, Kevin Irick1, Dongwha Shin2, Naehyuck Chang2 and Vijay Narayanan1
1PSU, US; 2Seoul National University, KR
Abstract
09:309.3.3ACTIVE-MODE LEAKAGE REDUCTION WITH DATA-RETAINED POWER GATING
Authors:
Andrew B. Kahng1, Seokhyeong Kang1 and Bongil Park2
1University of California, San Diego, US; 2Samsung Electronics, KR
Abstract
09:459.3.4A POWER-DRIVEN THERMAL SENSOR PLACEMENT ALGORITHM FOR DYNAMIC THERMAL MANAGEMENT
Authors:
Hai Wang1, Sheldon Tan2, Sahana Swarup2 and Xue-Xin Liu2
1University of Electronic Science and Technology of China, CN; 2University of California, Riverside, US
Abstract
10:00IP4-14, 704ACTIVE POWER-GATING-INDUCED POWER/GROUND NOISE ALLEVIATION USING PARASITIC CAPACITANCE OF ON-CHIP MEMORIES
Authors:
Xuan Wang1, Jiang Xu1, Wei Zhang2, Xiaowen Wu1, Yaoyao Ye1, Zhehui Wang1, Mahdi Nikdast1 and Zhe Wang1
1Hong Kong University of Science and Technology, HK; 2National University of Singapore, SG
Abstract
10:01IP4-15, 524ADAPTIVE THERMAL MANAGEMENT FOR PORTABLE SYSTEM BATTERIES BY FORCED CONVECTION COOLING
Authors:
Qing Xie1, Siyu Yue1, Donghwa Shin2, Naehyuck Chang2 and Massoud Pedram1
1University of Southern California, US; 2Seoul National University, KR
Abstract
10:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

9.4 Emerging Architectures

Date: Thursday 21 March 2013
Time: 08:30 - 10:00
Location / Room: Chartreuse

Chair:
Yvain Thonnart, CEA-LETI, FR

Co-Chair:
Michael Niemier, University of Notre Dame, US

This sesssion covers emerging architectures including 3D multi-core processors, reversible logic, and rotary oscillators.

TimeLabelPresentation Title
Authors
08:309.4.1SPARSE-ROTARY OSCILLATOR ARRAY(SROA) DESIGN FOR POWER AND SKEW REDUCTION
Authors:
Ying Teng and Baris Taskin, Drexel University, US
Abstract
09:009.4.2REVERSIBLE LOGIC SYNTHESIS OF K-INPUT, M-OUTPUT LOOKUP TABLES
Authors:
Alireza Shafaei, Mehdi Saeedi and Massoud Pedram, University of Southern California, US
Abstract
09:309.4.33D-MMC: A MODULAR 3D MULTI-CORE ARCHITECTURE WITH EFFICIENT RESOURCE POOLING
Authors:
Tiansheng Zhang1, Alessandro Cevrero2, Giulia Beanato2, Panagiotis Athanasopoulos2, Ayse Coskun1 and Yusuf Leblebici2
1Boston University, US; 2EPFL, CH
Abstract
10:00IP4-16, 58CACHE COHERENCE ENABLED ADAPTIVE REFRESH FOR VOLATILE STT-RAM
Authors:
Jianhua Li1, Liang Shi1, Qingan Li2, Chun Jason Xue3, Yiran Chen4 and Yinlong Xu1
1University of Science and Technology of China, CN; 2Wuhan University, CN; 3City University of Hong Kong, CN; 4University of Pittsburgh, US
Abstract
10:01IP4-17, 656IS TSV-BASED 3D INTEGRATION SUITABLE FOR INTER-DIE MEMORY REPAIR?
Authors:
Mihai Lefter, George Razvan Voicu, Mottaqiallah Taouil, Marius Enachescu, Said Hamdioui and Sorin Dan Cotofana, Delft University of Technology, NL
Abstract
10:02IP4-18, 747THERMOMECHANICAL STRESS-AWARE MANAGEMENT FOR 3D IC DESIGNS
Authors:
Qiaosha Zou1, Tao Zhang1, Eren Kursun2 and Yuan Xie1
1Pennsylvania State University, US; 2IBM Research, US
Abstract
10:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

9.5 Manufacturing and Design Security

Date: Thursday 21 March 2013
Time: 08:30 - 10:00
Location / Room: Meije

Chair:
Fresco Regazzoni, TU Delft / University of Lugano, CH

Co-Chair:
Patrick Schaumont, Virginia Tech, US

This session describes novel results in the manufacturing and operation of secure chips. The first paper addresses the risks in a secure manufacturing process, and presents a suitable countermeasure. A major risk in secure manufacturing is the insertion of hardware trojans in the design; the second and third paper describe detection techniques for such malicious insertions. The proposed techniques use delay measurements, and multi-modal characterization to achieve high detection probability despite the effects of manufacturing variation. An attacker may also target the design phase and steal intellectual property. The fourth paper introduces a reverse engineering technique to reconstruct a design from a low-level netlist. To answer these threats, we will need new tools and methods. The last paper in this session presents a design method to analyze timing-based security leaks in a design.

TimeLabelPresentation Title
Authors
08:309.5.1(Best Paper Award Candidate)
IS SPLIT MANUFACTURING SECURE?
Authors:
Jeyavijayan Rajendran1, Ozgur Sinanoglu2 and Ramesh Karri1
1Polytechnic Institue of New York University, US; 2New York University - Abu Dhabi, AE
Abstract
09:009.5.2TROJAN DETECTION VIA DELAY MEASUREMENTS: A NEW APPROACH TO SELECT PATHS AND VECTORS TO MAXIMIZE EFFECTIVENESS AND MINIMIZE COST
Authors:
Byeongju Cha and Sandeep K. Gupta, University of Southern California, US
Abstract
09:309.5.3HIGH-SENSITIVITY HARDWARE TROJAN DETECTION USING MULTIMODAL CHARACTERIZATION
Authors:
Kangqiao Hu1, Abdullah N. Nowroz2, Sherief Reda2 and Farinaz Koushanfar1
1Rice University, US; 2Brown University, US
Abstract
10:00IP4-19, 474REVERSE ENGINEERING DIGITAL CIRCUITS USING FUNCTIONAL ANALYSIS
Authors:
Pramod Subramanyan, Nestan Tsiskaridze, Kanika Pasricha, Dillon Reisman, Adriana Susnea and Sharad Malik, Princeton University, US
Abstract
10:01IP4-20, 181A PRACTICAL TESTING FRAMEWORK FOR ISOLATING HARDWARE TIMING CHANNELS
Authors:
Jason Oberg1, Sarah Meiklejohn1, Timothy Sherwood2 and Ryan Kastner1
1University of California, San Diego, US; 2University of California, Santa Barbara, US
Abstract
10:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

9.6 Improving IC Quality and Lifetime Though Advanced Characterization

Date: Thursday 21 March 2013
Time: 08:30 - 10:00
Location / Room: Bayard

Chair:
Rob Aitken, ARM, US

Co-Chair:
Mehdi Tahoori, Karlsruhe Institute of Technology, DE

Papers in this session address a broad range of challenges which we face in advanced technologies: how NAND flash ages and how this can be measured, how to ensure high yield for SRAM by doing very effective simulations, and an adaptive self-calibrating synchronizer that can cope with supply voltage, temperature and process variation.

TimeLabelPresentation Title
Authors
08:309.6.1THRESHOLD VOLTAGE DISTRIBUTION IN MLC NAND FLASH MEMORY: CHARACTERIZATION, ANALYSIS AND MODELING
Authors:
Yu Cai1, Erich Haratsch2, Onur Mutlu1 and Ken Mai1
1DSSC, Carnegie Mellon University, US; 2LSI Corporation, US
Abstract
09:009.6.2EFFICIENT IMPORTANCE SAMPLING FOR HIGH-SIGMA YIELD ANALYSIS WITH ADAPTIVE ONLINE SURROGATE MODELING
Authors:
Jian Yao, Zuochang Ye and Yan Wang, Tsinghua University, CN
Abstract
09:309.6.3METASTABILITY CHALLENGES FOR 65NM AND BEYOND; SIMULATION AND MEASUREMENTS
Authors:
Salomon Beer1, Ran Ginosar1, Jerome Cox2, Tom Chaney2 and Davis M. Zar2
1Technion, IL; 2Blendics, US
Abstract
10:00IP4-21, 477DESIGN AND IMPLEMENTATION OF AN ADAPTIVE PROACTIVE RECONFIGURATION TECHNIQUE FOR SRAM CACHES
Authors:
Peyman Pouyan, Esteve Amat, Francesc Moll and Antonio Rubio, Universitat Politècnica de Catalunya, ES
Abstract
10:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

9.7 Design and Scheduling

Date: Thursday 21 March 2013
Time: 08:30 - 10:00
Location / Room: Les Bans

Chair:
Stefan M. Petters, ISEP, PT

Co-Chair:
Benny Åkesson, TU Eindhoven, NL

This session present novel research finding on design and analysis technique for real-time systems. The first paper presents an achitecture for optimally configuring a multi-channel memory controller, so to reduce contention when accessing memory in a multi-processor on-chip system. The second paper presents a method for optimizing the scheduling parameters for a hierarchical scheduling system, where sub-systems can have different periods. The third paper presents a design methodology for code generation of real-time systems from synchronous FSM specifications. Finally, the last paper presents a real-time contention manager for transactional memory based systems.

TimeLabelPresentation Title
Authors
08:309.7.1ARCHITECTURE AND OPTIMAL CONFIGURATION OF A REAL-TIME MULTI-CHANNEL MEMORY CONTROLLER
Authors:
Manil Dev Gomony1, Benny Akesson2 and Kees Goossens1
1Eindhoven University of Technology, NL; 2Polytechnic Institute of Porto, PT
Abstract
09:009.7.2HOLISTIC DESIGN PARAMETER OPTIMIZATION OF MULTIPLE PERIODIC RESOURCES IN HIERARCHICAL SCHEDULING
Authors:
Man-Ki Yoon1, Jung-Eun Kim1, Richard Bradford2 and Lui Sha1
1University of Illinois at Urbana-Champaign, US; 2Rockwell Collins, US
Abstract
09:309.7.3ROBUST AND EXTENSIBLE TASK IMPLEMENTATION OF SYNCHRONOUS FINITE STATE MACHINES
Authors:
Qi Zhu1, Peng Deng1, Marco Di Natale2 and Haibo Zeng3
1University of California, Riverside, US; 2Scuola Superiore Sant'Anna, IT; 3McGill University, CA
Abstract
09:459.7.4FBLT: A REAL-TIME CONTENTION MANAGER WITH IMPROVED REAL-TIME SCHEDULABILITY
Authors:
Mohammed Elshambakey and Binoy Ravindran, Virginia Tech, US
Abstract
10:00IP4-22, 708A VIRTUAL PROTOTYPING PLATFORM FOR REAL-TIME SYSTEMS WITH A CASE STUDY FOR A TWO-WHEELED ROBOT
Authors:
Daniel Mueller-Gritschneder1, Kun Lu1, Erik Wallander1, Marc Greim1 and Ulf Schlichtmann2
1Technische Universitaet Muechen, DE; 2Technische Universität München, DE
Abstract
10:01IP4-23, 270SUFFICIENT REAL-TIME ANALYSIS FOR AN ENGINE CONTROL UNIT WITH CONSTANT ANGULAR VELOCITIES
Authors:
Victor Pollex1, Timo Feld1, Frank Slomka1, Ulrich Margull2, Ralph Mader3 and Gerhard Wirrer3
1Ulm University, DE; 2Ingolstadt University of Applied Sciences, DE; 3Continental, DE
Abstract
10:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

IP4 Interactive Presentations

Date: Thursday 21 March 2013
Time: 10:00 - 10:30
Location / Room: Exhibition Hall (espace accueil)

Interactive Presentations run simulatenously during a 30-minute slot. A poster associated to the IP paper is on display throughout the morning. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session, prior to the actual Interactive Presentation.

LabelPresentation Title
Authors
IP4-1EFFICIENT AND SCALABLE OPENMP-BASED SYSTEM-LEVEL DESIGN
Authors:
Alessandro Cilardo, Luca Gallo, Antonino Mazzeo and Nicola Mazzocca, University of Naples Federico II, IT
Abstract
IP4-2UTILIZING VOLTAGE-FREQUENCY ISLANDS IN C-TO-RTL SYNTHESIS FOR STREAMING APPLICATIONS
Authors:
Xinyu He1, Shuangchen Li1, Yongpan Liu1, X. Sharon Hu2 and Huazhong Yang1
1Tsinghua University, CN; 2University of Notre Dame, US
Abstract
IP4-3BICONDITIONAL BDD: A NOVEL CANONICAL BDD FOR LOGIC SYNTHESIS TARGETING XOR-RICH CIRCUITS
Authors:
Luca Amarú, Pierre-Emmanuel Gaillardon and Giovanni De Micheli, EPFL, CH
Abstract
IP4-4OPTIMIZING BDDS FOR TIME-SERIES DATASET MANIPULATION
Authors:
Stergios Stergiou and Jawahar Jain, Fujitsu, US
Abstract
IP4-5INCORPORATING THE IMPACTS OF WORKLOAD-DEPENDENT RUNTIME VARIATIONS INTO TIMING ANALYSIS
Authors:
Farshad Firouzi1, Saman Kiamehr1, Sani Nassif2 and Mehdi Tahoori1
1Karlsruhe Institute of Technology, DE; 2IBM, US
Abstract
IP4-6AN AREA-EFFICIENT NETWORK INTERFACE FOR A TDM-BASED NETWORK-ON-CHIP
Authors:
Jens Sparsø, Evangelia Kasapaki and Martin Schoeberl, Technical University of Denmark, DK
Abstract
IP4-7CARS: CONGESTION-AWARE REQUEST SCHEDULER FOR NETWORK INTERFACES IN NOC-BASED MANYCORE SYSTEMS
Authors:
Masoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila and Hannu Tenhunen, University of Turku, FI
Abstract
IP4-8A FAST AND EFFICIENT DFT FOR TEST AND DIAGNOSIS OF POWER SWITCHES IN SOCS
Authors:
Xiaoyu Huang, Jimson Mathew, Rishad A Shafik, Subhashish Bhattacharjee and Dhiraj K Pradhan, University of Bristol, UK
Abstract
IP4-9MULTIRATE CONTROLLER DESIGN FOR RESOURCE- AND SCHEDULE-CONSTRAINED AUTOMOTIVE ECUS
Authors:
Dip Goswami1, Alejandro Masrur1, Reinhard Schneider1, Chun Jason Xue2 and Samarjit Chakraborty1
1Technische Universität München, DE; 2City University of Hong Kong, HK
Abstract
IP4-10DESIGN OF AN ULTRA-LOW POWER DEVICE FOR AIRCRAFT STRUCTURAL HEALTH MONITORING
Authors:
Alessandro Perelli1, Carlo Caione1, Luca De Marchi1, Davide Brunelli2, Alessandro Marzani1 and Luca Benini1
1University of Bologna, IT; 2University of Trento, IT
Abstract
IP4-11(Best Paper Award Candidate)
FAST AND ACCURATE TLM SIMULATIONS USING TEMPORAL DECOUPLING FOR FIFO-BASED COMMUNICATIONS
Authors:
Claude Helmstetter1, Jérôme Cornet2, Matthieu Moy3, Pascal Vivet1 and Bruno Galilée2
1CEA-Leti, FR; 2STMicroelectronics, FR; 3Verimag, FR
Abstract
IP4-12DETERMINING RELEVANT MODEL ELEMENTS FOR THE VERIFICATION OF UML/OCL SPECIFICATIONS
Authors:
Julia Seiter, Robert Wille, Mathias Soeken and Rolf Drechsler, University of Bremen, DE
Abstract
IP4-13TOWARDS A GENERIC VERIFICATION METHODOLOGY FOR SYSTEM MODELS
Authors:
Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann and Rolf Drechsler, University of Bremen, DE
Abstract
IP4-14ACTIVE POWER-GATING-INDUCED POWER/GROUND NOISE ALLEVIATION USING PARASITIC CAPACITANCE OF ON-CHIP MEMORIES
Authors:
Xuan Wang1, Jiang Xu1, Wei Zhang2, Xiaowen Wu1, Yaoyao Ye1, Zhehui Wang1, Mahdi Nikdast1 and Zhe Wang1
1Hong Kong University of Science and Technology, HK; 2National University of Singapore, SG
Abstract
IP4-15ADAPTIVE THERMAL MANAGEMENT FOR PORTABLE SYSTEM BATTERIES BY FORCED CONVECTION COOLING
Authors:
Qing Xie1, Siyu Yue1, Donghwa Shin2, Naehyuck Chang2 and Massoud Pedram1
1University of Southern California, US; 2Seoul National University, KR
Abstract
IP4-16CACHE COHERENCE ENABLED ADAPTIVE REFRESH FOR VOLATILE STT-RAM
Authors:
Jianhua Li1, Liang Shi1, Qingan Li2, Chun Jason Xue3, Yiran Chen4 and Yinlong Xu1
1University of Science and Technology of China, CN; 2Wuhan University, CN; 3City University of Hong Kong, CN; 4University of Pittsburgh, US
Abstract
IP4-17IS TSV-BASED 3D INTEGRATION SUITABLE FOR INTER-DIE MEMORY REPAIR?
Authors:
Mihai Lefter, George Razvan Voicu, Mottaqiallah Taouil, Marius Enachescu, Said Hamdioui and Sorin Dan Cotofana, Delft University of Technology, NL
Abstract
IP4-18THERMOMECHANICAL STRESS-AWARE MANAGEMENT FOR 3D IC DESIGNS
Authors:
Qiaosha Zou1, Tao Zhang1, Eren Kursun2 and Yuan Xie1
1Pennsylvania State University, US; 2IBM Research, US
Abstract
IP4-19REVERSE ENGINEERING DIGITAL CIRCUITS USING FUNCTIONAL ANALYSIS
Authors:
Pramod Subramanyan, Nestan Tsiskaridze, Kanika Pasricha, Dillon Reisman, Adriana Susnea and Sharad Malik, Princeton University, US
Abstract
IP4-20A PRACTICAL TESTING FRAMEWORK FOR ISOLATING HARDWARE TIMING CHANNELS
Authors:
Jason Oberg1, Sarah Meiklejohn1, Timothy Sherwood2 and Ryan Kastner1
1University of California, San Diego, US; 2University of California, Santa Barbara, US
Abstract
IP4-21DESIGN AND IMPLEMENTATION OF AN ADAPTIVE PROACTIVE RECONFIGURATION TECHNIQUE FOR SRAM CACHES
Authors:
Peyman Pouyan, Esteve Amat, Francesc Moll and Antonio Rubio, Universitat Politècnica de Catalunya, ES
Abstract
IP4-22A VIRTUAL PROTOTYPING PLATFORM FOR REAL-TIME SYSTEMS WITH A CASE STUDY FOR A TWO-WHEELED ROBOT
Authors:
Daniel Mueller-Gritschneder1, Kun Lu1, Erik Wallander1, Marc Greim1 and Ulf Schlichtmann2
1Technische Universitaet Muechen, DE; 2Technische Universität München, DE
Abstract
IP4-23SUFFICIENT REAL-TIME ANALYSIS FOR AN ENGINE CONTROL UNIT WITH CONSTANT ANGULAR VELOCITIES
Authors:
Victor Pollex1, Timo Feld1, Frank Slomka1, Ulrich Margull2, Ralph Mader3 and Gerhard Wirrer3
1Ulm University, DE; 2Ingolstadt University of Applied Sciences, DE; 3Continental, DE
Abstract

UB09 Session 9

Date: Thursday 21 March 2013
Time: 10:00 - 12:00
Location / Room: Booth 46, Exhibition

TimeLabelPresentation Title
Authors
10:00UB09.1USB STARGATE: AN OPEN-SOURCE HARDWARE DEVICE FOR HUMAN COMPUTER INTERACTION
Authors:
Pablo Viana1, Raiann Dias1 and Lucas Torquato2
1UFAL, BR; 2UFPE, BR
Abstract
10:00UB09.2EDA TOOLS FOR DEPENDABLE SYSTEM DESIGN METHODOLOGY
Authors:
Ken Yano, Mitsugu Ogawa, Ryota Yoshinaga, Takahito Yoshiki, Takanori Hayashida and Toshinori Sato, Fukuoka University, JP
Abstract
10:00UB09.3COMBINING APPLICATION ADAPTIVITY AND SYSTEM-WIDE RESOURCE MANAGEMENT: A NOVEL APPROACH
Authors:
Edoardo Paone, Giuseppe Massari, Patrick Bellasi, William Fornaciari, Gianluca Palermo, Cristina Silvano and Vittorio Zaccaria, Politecnico di Milano, IT
Abstract
10:00UB09.4TACP: TEST AND CHARACTERIZATION PLATFORM
Authors:
Muhammad Elrabaa and Amran Al-Aghbari, King Fahd University of Petroleum and Minerals, SA
Abstract
10:00UB09.5FUNCTIONAL VERIFICATION OF CUSTOM PROCESSORS USING AUTOMATED GENERATION OF VERIFICATION ENVIRONMENTS
Authors:
Marcela Šimková, Zdeněk Přikryl, Zdeněk Kotásek and Tomáš Hruška, Faculty of Information Technology, Brno University of Technology, CZ
Abstract
10:00UB09.6FT-UNSHADES2 A FLEXIBLE FAULT INJECTION FRAMEWORK
Authors:
Juan Mogollón and Hipolito Guzman, University of Sevilla, ES
Abstract
10:00UB09.7SM2DEA: FROM MATLAB-SIMULINK TO DISTRIBUTED EMBEDDED APPLICATIONS: AN AUTOMOTIVE TOOL DEMONSTRATION
Authors:
Günter Ehmen1, Matthias Büker2, Stefan Henkler2, Achim Rettberg1, Ingo Stierand1 and Eike Thaden2
1Carl von Ossietzky University of Oldenburg, DE; 2OFFIS, DE
Abstract
10:00UB09.8HIERARCHICAL ESL FAULT SIMULATION PACKAGE
Authors:
Somayeh Sadeghi-Kohan1, Arash Akhoundi1, Farnaz Forooghifar1, Elmira Karimi2, Mohammad Ghasemi1, Zahra Najafi1, Saba Amanollahi3 and Zain Navabi1
1University of Tehran, IR; 2Sharif University, IR; 3Shahid Beheshti University, IR
Abstract
10:00UB09.9ECA : AN INTEGRATED USER-FRIENDLY TOOL FOR EDUCATION OF COMPUTER ARITHMETIC
Authors:
Saba Amanollahi, Hamed Fatemi and Ghassem Jaberipur, Shahid Beheshti University, IR
Abstract
12:00End of session
12:30Lunch Break in Ecrins
Buffet lunch (Eat early for Smart Cities and Communities Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/11.0)

10.1 SPECIAL DAY on "Electronic Technologies for Smart Cities" - HOT TOPIC: Smart Data Centers Design and Optimization

Date: Thursday 21 March 2013
Time: 11:00 - 12:30
Location / Room: Oisans

Organiser:
David Atienza, EPFL, CH

Chair:
Roman Hermida, UCM, ES

Co-Chair:
Ayse K. Coskun, Boston University, US

This special session presents an overview of some of the hottest research topics towards the conception of future smart and energy-efficient datacenters. The first presentation explores the limits in the conception of highly dense datacenter infrastructures under current and future energy constraints. The second presentation presents smart energy-aware allocation techniques in virtualized datacenters to maximize the use of free cooling. The third presentation explores the limits of energy-efficient servers and resources utilization in next-generation computing systems for datacenters.

TimeLabelPresentation Title
Authors
11:0010.1.1ROADMAP TOWARDS ULTIMATELY EFFICIENT ZETA-SCALE DATACENTERS
Authors:
Patrick Ruch1, Thomas Brunschwiler2, Stephan Paredes2, Bruno Michel1 and Ingmar Meijer3
1IBM, US; 2IBM, CH; 3IBM,
Abstract
11:3010.1.2CORRELATION-AWARE VIRTUAL MACHINE ALLOCATION FOR ENERGY-EFFICIENT DATACENTERS
Authors:
Jungsoo Kim1, Martino Ruggiero1, David Atienza1 and Marcel Lederberger2
1EPFL, CH; 2Credit Suisse, CH
Abstract
12:0010.1.3RESOURCE EFFICIENT COMPUTING FOR WAREHOUSE-SCALE DATACENTERS
Author:
Christos Kozyrakis, Stanford University, US
Abstract
12:30End of session
Lunch Break in Ecrins
Buffet lunch (Eat early for Smart Cities and Communities Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/11.0)

10.2 EMBEDDED TUTORIAL: On the Use of GP-GPUs for Accelerating Computing-Intensive EDA Applications

Date: Thursday 21 March 2013
Time: 11:00 - 12:30
Location / Room: Belle-Etoile

Organiser:
Franco Fummi, University of Verona, IT

Chair:
Franco Fummi, University of Verona, IT

Co-Chair:
Florian Letombe, SpringSoft, FR

General purpose graphics processing units (GP-GPUs) have recently been explored as a new computing paradigm for accelerating computation intensive EDA applications. Such many-core architectures have been applied for (i) accelerating both logic and fault simulation of HDL designs, (ii) accelerating simulation of such designs described both at RTL and Gate level, (iii) accelerating SystemC simulation. This embedded tutorial presents a comprehensive analysis of the best results obtained by adopting GP-GPUs in all these EDA applications.

TimeLabelPresentation Title
Authors
11:0010.2.1ON THE USE OF GP-GPUS FOR ACCELERATING LOGIC SIMULATION
Authors:
Valeria Bertacco and Debapriya Chatterjee, University of Michigan, US
Abstract
11:3010.2.2ACCELERATING RTL SIMULATION WITH GP-GPUS: CUDA VS. OPENCL
Authors:
Nicola Bombieri and Sara Vinco, University of Verona, IT
Abstract
12:0010.2.3PARALLELIZING SYSTEMC SIMULATIONS ACROSS CPUS AND GPUS
Author:
Hiren Patel, University of Waterloo, CA
Abstract
12:30End of session
Lunch Break in Ecrins
Buffet lunch (Eat early for Smart Cities and Communities Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/11.0)

10.3 Thermal Analysis and Power Optimization Techniques

Date: Thursday 21 March 2013
Time: 11:00 - 12:30
Location / Room: Stendahl

Chair:
Siddharth Garg, University of Waterloo, CA

Co-Chair:
Yiran Chen, University of Pittsburgh, US

The circuit reliability is greatly impacted by its thermal profile and power consumption. This session starts with the power optimization and lifetime enhancements for modern VLSI circuits, followed by thermal analysis and simulation methods of 3D ICs.

TimeLabelPresentation Title
Authors
11:0010.3.1SUBSTITUTE-AND-SIMPLIFY: A UNIFIED DESIGN PARADIGM FOR APPROXIMATE AND QUALITY CONFIGURABLE CIRCUITS
Authors:
Swagath Venkataramani, Kaushik Roy and Anand Raghunathan, Purdue University, US
Abstract
11:3010.3.2ENHANCING MULTICORE RELIABILITY THROUGH WEAR COMPENSATION IN ONLINE ASSIGNMENT AND SCHEDULING
Authors:
Thidapat Chantem1, Yun Xiang2, X. Sharon Hu3 and Robert P. Dick2
1Utah State University, US; 2University of Michigan, US; 3University of Notre Dame, US
Abstract
12:0010.3.3NUMANA: A HYBRID NUMERICAL AND ANALYTICAL THERMAL SIMULATOR FOR 3-D ICS
Authors:
Yu-Min Lee1, Tsung-Heng Wu1, Pei-Yu Huang2 and Chi-Ping Yang1
1National Chiao Tung University, TW; 2Industrial Technology Research Institute, TW
Abstract
12:1510.3.4EXPLICIT TRANSIENT THERMAL SIMULATION OF LIQUID-COOLED 3D ICS
Authors:
Alain Fourmigue, Giovanni Beltrame and Gabriela Nicolescu, École Polytechnique de Montréal, CA
Abstract
12:30IP5-1, 793MITIGATING DARK SILICON PROBLEMS USING SUPERLATTICE-BASED THERMOELECTRIC COOLERS
Authors:
Francesco Paterna and Sherief Reda, Brown University, US
Abstract
12:31IP5-2, 113RUN-TIME PROBABILISTIC DETECTION OF MISCALIBRATED THERMAL SENSORS IN MANY-CORE SYSTEMS
Authors:
Jia Zhao, Shiting (Justin) Lu, Wayne Burleson and Russell Tessier, University of Massachusetts Amherst, US
Abstract
12:30End of session
Lunch Break in Ecrins
Buffet lunch (Eat early for Smart Cities and Communities Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/11.0)

10.4 Abstraction Techniques and SAT/SMT-Based Optimizations

Date: Thursday 21 March 2013
Time: 11:00 - 12:30
Location / Room: Chartreuse

Chair:
Fahim Rahim, Atrenta, FR

Co-Chair:
Julian Schmaltz, Open University of the Netherlands, NL

Automatically computing abstractions of large circuits combined with powerful SAT and SMT solvers is key to the success of formal verification techniques. The papers of this session present significant improvements in abstraction techniques and SAT/SMT-based optimizations. SAT- and SMT-abstractions are guided by unsatisfiable cores. Three papers address the issue of reducing the size of interpolants generated during the construction of abstractions. The second paper proposes a new abstraction technique demonstrating a significant improvement in gate-level abstractions.

TimeLabelPresentation Title
Authors
11:0010.4.1(Best Paper Award Candidate)
GLA: GATE-LEVEL ABSTRACTION REVISITED
Authors:
Alan Mishchenko1, Niklas Een1, Robert Brayton1, Jason Baumgartner2, Hari Mony2 and Pradeep Nalla3
1University of California, Berkeley, US; 2IBM, US; 3IBM, IN
Abstract
11:3010.4.2LEMMA LOCALIZATION: A PRACTICAL METHOD FOR DOWNSIZING SMT-INTERPOLANTS
Authors:
Florian Pigorsch and Christoph Scholl, University of Freiburg, DE
Abstract
12:0010.4.3CORE MINIMIZATION IN SAT-BASED ABSTRACTION
Authors:
Anton Belov1, Huan Chen1, Alan Mishchenko2 and Joao Marques-Silva1
1University College Dublin, IE; 2University of California, Berkeley, US
Abstract
12:1510.4.4OPTIMIZATION TECHNIQUES FOR CRAIG INTERPOLANT COMPACTION IN UNBOUNDED MODEL CHECKING
Authors:
Gianpiero Cabodi, Carmelo Loiacono and Danilo Vendraminetto, Politecnico di Torino, IT
Abstract
12:30IP5-3, 654FORMAL ANALYSIS OF STEADY STATE ERRORS IN FEEDBACK CONTROL SYSTEMS USING HOL-LIGHT
Authors:
Osman Hasan and Muhammad Ahmad, National University of Sciences and Technology, PK
Abstract
12:31IP5-4, 734A NOVEL CONCURRENT CACHE-FRIENDLY BINARY DECISION DIAGRAM CONSTRUCTION FOR MULTI-CORE PLATFORMS
Authors:
Mahmoud El-Bayoumi1, Michael Hsiao1 and Mustafa ElNainay2
1Virginia Tech, US; 2Alexanderia University, EG
Abstract
12:30End of session
Lunch Break in Ecrins
Buffet lunch (Eat early for Smart Cities and Communities Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/11.0)

10.5 Design and Verification of Mixed-Signal Circuits

Date: Thursday 21 March 2013
Time: 11:00 - 12:30
Location / Room: Meije

Chair:
Catherine Dehollain, EPFL, CH

Co-Chair:
Gunhan Dundar, Bogazici University, TR

Some key questions in mixed-signal design are low-power design, modeling, and verification. This session addresses design of low power, low-voltage sensor interfaces as well as non-linear model extraction of analogue circuits and statistical MOSFET models. On the verification front, formal verification of analogue circuits and reachability analysis of non-linear circuits are discussed.

TimeLabelPresentation Title
Authors
11:0010.5.1A LOW-POWER AND LOW-VOLTAGE BBPLL-BASED SENSOR INTERFACE IN 130NM CMOS FOR WIRELESS SENSOR NETWORKS
Authors:
Jelle Van Rethy, Hans Danneels, Valentijn De Smedt, Wim Dehaene and Georges Gielen, KU Leuven, BE
Abstract
11:3010.5.2(Best Paper Award Candidate)
REACHABILITY ANALYSIS OF NONLINEAR ANALOG CIRCUITS THROUGH ITERATIVE REACHABLE SET REDUCTION
Authors:
Seyed Nematollah Ahmadyan and Shobha Vasudevan, University of Illinois at Urbana-Champaign, US
Abstract
12:0010.5.3FORMAL VERIFICATION OF ANALOG CIRCUIT PARAMETERS ACROSS VARIATION UTILIZING SAT
Authors:
Merritt Miller and Forrest Brewer, University of California, Santa Barbara, US
Abstract
12:1510.5.4EXTRACTING ANALYTICAL NONLINEAR MODELS FROM ANALOG CIRCUITS BY RECURSIVE VECTOR FITTING OF TRANSFER FUNCTION TRAJECTORIES
Authors:
Dimitri De Jonghe1, Dirk Deschrijver2, Tom Dhaene2 and Georges Gielen1
1KU Leuven, BE; 2University of Ghent, BE
Abstract
12:30IP5-5, 364STATISTICAL MODELING WITH THE VIRTUAL SOURCE MOSFET MODEL
Authors:
Li Yu1, Lan Wei1, Dimitri Antoniadis1, Ibrahim Elfadel2 and Duane Boning1
1Massachusetts Institute of Technology, US; 2Masdar Institute of Science and Technology, AE
Abstract
12:31IP5-6, 723AUTOMATIC CIRCUIT SIZING TECHNIQUE FOR THE ANALOG CIRCUITS WITH FLEXIBLE TFTS CONSIDERING PROCESS VARIATION AND BENDING EFFECTS
Authors:
Yen-Lung Chen, Wan-Rong Wu, Guan-Ruei Lu and Chien-Nan Jimmy Liu, National Central University, TW
Abstract
12:30End of session
Lunch Break in Ecrins
Buffet lunch (Eat early for Smart Cities and Communities Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/11.0)

10.6 On-Line Testing Techniques

Date: Thursday 21 March 2013
Time: 11:00 - 12:30
Location / Room: Bayard

Chair:
Cecilia Metra, University of Bologna, IT

Co-Chair:
Cristiana Bolchini, Politecnico Di Milano, IT

This session proposes several approaches for on-line testing and analysis of in-core components such as register files and memory sub-systems.

TimeLabelPresentation Title
Authors
11:0010.6.1ON-LINE FUNCTIONALLY UNTESTABLE FAULT IDENTIFICATION IN EMBEDDED PROCESSOR CORES
Authors:
Paolo Bernardi1, Ernesto Sanchez1, Matteo Sonza Reorda1, Oscar Ballan2 and Matteo Bonazza1
1Politecnico di Torino, IT; 2STMicroelectronics, IT
Abstract
11:3010.6.2CAPTURING VULNERABILITY VARIATIONS FOR REGISTER FILES
Authors:
Xavier Vera1, Javier Carretero1, Enric Herrero1, Matteo Monchiero2 and Tanausu Ramirez1
1Intel, ES; 2Intel, IT
Abstract
12:0010.6.3ERROR DETECTION IN TERNARY CAMS USING BLOOM FILTERS
Authors:
Salvatore Pontarelli1, Marco Ottavi1, Adrian Evans2 and Shi-Jie Wen3
1University of Rome "Tor Vergata", IT; 2Cisco Systems, CA; 3Cisco Systems, US
Abstract
12:1510.6.4AVF-DRIVEN PARITY OPTIMIZATION FOR MBU PROTECTION OF IN-CORE MEMORY ARRAYS
Authors:
Michail Maniatakos1, Maria Michael2 and Yiorgos Makris3
1New York University Abu Dhabi, AE; 2University of Cyprus, CY; 3University of Texas at Dallas, US
Abstract
12:30IP5-7, 320AN ENHANCED DOUBLE-TSV SCHEME FOR DEFECT TOLERANCE IN 3D-IC
Authors:
Hsiu-Chuan Shih and Cheng-Wen Wu, National Tsing Hua University, TW
Abstract
12:31IP5-8, 324MEMPACK: AN ORDER OF MAGNITUDE REDUCTION IN THE COST, RISK, AND TIME FOR MEMORY COMPILER CERTIFICATION
Authors:
Kartik Mohanram1, Matthew Wartell1 and Sundar Iyer2
1University of Pittsburgh, US; 2Memoir Systems, US
Abstract
12:32IP5-9, 987EXPLOITING REPLICATED CHECKPOINTS FOR SOFT ERROR DETECTION AND CORRECTION
Authors:
Fahrettin Koc, Kenan Bozdas, Burak Karsli and Oguz Ergin, TOBB University of Economics and Technology, TR
Abstract
12:30End of session
Lunch Break in Ecrins
Buffet lunch (Eat early for Smart Cities and Communities Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/11.0)

10.7 Embedded Software for Many-Core Architectures

Date: Thursday 21 March 2013
Time: 11:00 - 12:30
Location / Room: Les Bans

Chair:
Oliver Bringmann, University of Tuebingen, DE

Co-Chair:
Sébastien Le Beux, Lyon Institute of Nanotechnology, FR

This session deals with parallel programming models and scheduling. The first paper employs game theory to decentralized task migration for execution speed-up and fault tolerance. The other three papers propose parallel-programming models and scheduling approaches for software pipelines, fine-grained OpenMP, and asynchronous joining of forked tasks, respectively.

TimeLabelPresentation Title
Authors
11:0010.7.1(Best Paper Award Candidate)
GAME-THEORETIC ANALYSIS OF DECENTRALIZED CORE ALLOCATION SCHEMES ON MANY-CORE SYSTEMS
Authors:
Stefan Wildermann, Tobias Ziermann and Jürgen Teich, University of Erlangen-Nuremberg, DE
Abstract
11:3010.7.2ENABLING FINE-GRAINED OPENMP TASKING ON TIGHTLY-COUPLED SHARED MEMORY CLUSTERS
Authors:
Paolo Burgio, Giuseppe Tagliavini, Andrea Marongiu and Luca Benini, University of Bologna, IT
Abstract
12:0010.7.3ARTM: A LIGHTWEIGHT FORK-JOIN FRAMEWORK FOR MANYCORE EMBEDDED SYSTEMS
Authors:
Maroun Ojail, Raphaël David, Yves Lhuillier and Alexandre Guerre, CEA LIST, FR
Abstract
12:1510.7.4PIPELETS: SELF-ORGANIZING SOFTWARE PIPELINES FOR MANY CORE ARCHITECTURES
Authors:
Janmartin Jahn and Jörg Henkel, Karlsruhe Institute of Technology, DE
Abstract
12:30IP5-10, 406AN INTEGRATED APPROACH FOR MANAGING THE LIFETIME OF FLASH-BASED SSDS
Authors:
Sungjin Lee, Taejin Kim, Ji-Sung Park and Jihong Kim, Seoul National University, KR
Abstract
12:30End of session
Lunch Break in Ecrins
Buffet lunch (Eat early for Smart Cities and Communities Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/11.0)

10.8 PANEL: Will 3D-IC Remain a Technology of the Future… Even in the Future?

Date: Thursday 21 March 2013
Time: 11:00 - 12:30
Location / Room: Lesdigiueres (Exhibition Theatre)

Organiser:
Marco Casale-Rossi, Synopsys, US

Chair:
Giovanni De Micheli, EPFL, CH

Co-Chair:
Marco Casale-Rossi, Synopsys, US

If asked "who needs faster planes?" the vast majority of the 2.75 billion airline passengers (source: IATA 2011) would say that they do need faster planes, and that they need them right now. Still, the commercial aircrafts cruising speed has remained the same - 800 km/hour - over the last 50+ years, and after the sad end of the Concorde project, neither Airbus nor Boeing are seriously working on the topic. Along the same lines, when asked "who needs 3D-IC?", most IC designers say that they desperately need 3D-IC to keep advancing electronic products performance, whilst addressing the needs of higher bandwidth, lower cost, heterogeneous integration, and power constraints. Still, 3D-IC continues to be the technology of the future. What are the road blocks towards 3D-IC adoption? Is it process technology, foundry or OSAT commercial offering, or EDA, or the business economics that is holding 3D-IC on the ground? In the introductory presentation of this panel session, LETI Patrick Leduc will illustrate the state-of-the-art of commercial, mainstream 3D-IC. EPFL Professor Giovanni de Micheli will moderate an industry and research panel, to understand what are the key factors preventing 3D-IC from becoming the technology of today.

Panelists:

  • Patrick Blouet, ST-Ericsson, FR
  • Brendan Farley, Xilinx, IE
  • Anna Fontanelli, Monozukuri, IT
  • Patrick Leduc, LETI, FR
  • Dragomir Milojevic, IMEC, BE
  • Steve Smith, Synopsys, US
12:30End of session
Lunch Break in Ecrins
Buffet lunch (Eat early for Smart Cities and Communities Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/11.0)

UB10 Session 10

Date: Thursday 21 March 2013
Time: 12:00 - 14:00
Location / Room: Booth 46, Exhibition

TimeLabelPresentation Title
Authors
12:00UB10.1THE MATISSE MATLAB COMPILER
Authors:
João Cardoso1, João Bispo1, Pedro Pinto1, Ricardo Nobre1, Tiago Carvalho1 and Pedro Diniz2
1University of Porto, PT; 2INESC-ID, PT
Abstract
12:00UB10.2SYNTHORUS-2: AUTOMATIC PROTOTYPING ON FPGA FROM PSL
Authors:
Fatemeh Javaheri, Katell Morin‐Allory, Alexandre Porcher and Dominique Borrione, TIMA Lab, FR
Abstract
12:00UB10.3FPGA-BASED IN SYSTEM MULTIPLE LRU CACHE SIMULATION
Authors:
Josef Schneider, Jorgen Peddersen and Sridevan Parameswaran, University of New South Wales, AU
Abstract
12:00UB10.4FLEXIBLE AND HIGH-SPEED SYSTEM-LEVEL PERFORMANCE ANALYSIS USING HARDWARE-ACCELERATED SIMULATION
Authors:
Sascha Bischoff1, Andreas Sandberg2, Andreas Hansson3, Dam Sunwoo4, Ali G. Saidi4, Matthew Horsnell3 and Bashir M. Al-Hashimi1
1University of Southampton, UK; 2Uppsala University, SE; 3ARM, UK; 4ARM, US
Abstract
12:00UB10.5EDA FOR SYSTEM LEVEL VERIFICATION: AN ADAPTIVE SYSTEM LEVEL VERIFICATION ENVIRONMENT
Authors:
Hassan Sohofi and Zainalabedin Navabi, University of Tehran, IR
Abstract
12:00UB10.6DAEDALUS^RT: A DESIGN FLOW FOR HARD-REAL-TIME EMBEDDED STREAMING SYSTEMS
Authors:
Mohamed Bamakhrama, Jiali Teddy Zhai, Sven van Haastregt and Todor Stefanov, Leiden University, NL
Abstract
12:00UB10.7SYNTHESIZING ABSTRACT COMMUNICATIONS TO RTL STANDARD BUS STRUCTURES
Authors:
Somayeh Sadeghi-Kohan, Rasoul Jafari, Ghazaleh Vazhbakht, Parastoo Kamranfar, Reza Namazian, Mahya Saffarpour and Zain Navabi, University of Tehran, IR
Abstract
12:00UB10.8HIERARCHICAL ESL FAULT SIMULATION PACKAGE
Authors:
Somayeh Sadeghi-Kohan1, Arash Akhoundi1, Farnaz Forooghifar1, Elmira Karimi2, Mohammad Ghasemi1, Zahra Najafi1, Saba Amanollahi3 and Zain Navabi1
1University of Tehran, IR; 2Sharif University, IR; 3Shahid Beheshti University, IR
Abstract
12:00UB10.9PONG: APPLICATION FOR TEACHING CHIP DESIGN
Authors:
Armin Gruenewald, Matthias Mielke and Rainer Brück, University of Siegen, DE
Abstract
14:00End of session
15:30Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

11.0 Special Day Keynote on "Electronic Technologies for Smart Cities"

Date: Thursday 21 March 2013
Time: 13:30 - 14:00
Location / Room: Oisans

TimeLabelPresentation Title
Authors
13:3010.1.2.1SMART CITIES AND COMMUNITIES AT THE REGIONAL, NATIONAL AND EUROPEAN LEVELS
Author:
Francesco Profumo, Italian Minister of Education, University and Research and Genevieve Fioraso, French Minister for Higher Education and Research (To Be Confirmed),
14:00End of session
15:30Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

11.1 SPECIAL DAY on "Electronic Technologies for Smart Cities" - HOT TOPIC: Smart Health

Date: Thursday 21 March 2013
Time: 14:00 - 15:35
Location / Room: Oisans

Organisers:
Alberto Sangiovanni Vincentelli, University of California, Berkeley, US
Daniela De Venuto, Politecnico di Bari, IT

Chair:
Daniela De Venuto, Politecnico di Bari, IT

Co-Chair:
Alberto Sangiovanni Vincentelli, University of California, Berkeley, US

The Smart Health session is about fundamental technical and scientific advances that may change radically the way healthcare is conceived today. Longer life expectation, aging, overweight and pollution are among factors that pose severe challenges to healthcare and its sustainability. Wireless devices, brain-machine interfaces, and cognitive process models may provide potential solutions to a vast array of problems involving clinical and human aspects, as well as economics and social issues. The presenters will introduce and discuss some aspects of devices and technologies that are essential in defining new approaches to healthcare and human well-being.

TimeLabelPresentation Title
Authors
14:0011.1.1DR. FRANKENSTEIN'S DREAM MADE POSSIBLE: IMPLANTED ELECTRONIC DEVICES
Authors:
Daniela De Venuto1 and Alberto Sangiovanni Vincentelli2
1Politecnico di Bari, IT; 2University of California, Berkeley, US
Abstract
14:2011.1.2ADDRESSING THE HEALTHCARE COST DILEMMA BY MANAGING HEALTH INSTEAD OF MANAGING ILLNESS - AN OPPORTUNITY FOR WIRELESS WEARABLE SENSORS
Authors:
Chris Van Hoof1 and Julien Penders2
1IMEC, BE; 2IMEC/Holst Centrum, NL
Abstract
14:4511.1.3ELECTRONIC IMPLANTS: POWER DELIVERY AND MANAGEMENT
Authors:
Jacopo Olivo, Sara S. Ghoreishizadeh, Sandro Carrara and Giovanni De Micheli, EPFL, CH
Abstract
15:1011.1.4CYBORG INSECTS, NEURAL INTERFACES AND OTHER THINGS: BUILDING INTERFACES BETWEEN THE SYNTHETIC AND THE MULTICELLULAR
Authors:
J. Van Kleef, T. Massey, P. Ledochowitsch, R. Muller, R. Tiefenauer, T. Blanche, Hirotaka Sato and Michel M. Maharabiz, University of California, Berkeley, US
Abstract
15:35End of session

11.2 High-Level Synthesis and Coarse-Grained Reconfigurable Architectures

Date: Thursday 21 March 2013
Time: 14:00 - 15:30
Location / Room: Belle-Etoile

Chair:
Philippe Coussy, Université de Bretagne-Sud, FR

Co-Chair:
Fadi Kurdahi, University of California Irvine, US

The first paper investigates the impact of simultaneous scheduling and binding in high-level synthesis. The second paper improves latency by performing high-level code transformation with Taylor Expansion Diagrams. The thirth paper presents a platform based on custom reconfigurable arrays for multi-processor systems exploiting instruction- and thread-level parallelism.The fourth paper proposes a high-level modelling tool chain for embedded FPGAs.

TimeLabelPresentation Title
Authors
14:0011.2.1SHARE WITH CARE: A QUANTITATIVE EVALUATION OF SHARING APPROACHES IN HIGH-LEVEL SYNTHESIS
Authors:
Alex Kondratyev, Luciano Lavagno, Mike Meyer and Yosinori Watanabe, Cadence Design Systems, US
Abstract
14:3011.2.2FPGA LATENCY OPTIMIZATION USING SYSTEM-LEVEL TRANSFORMATIONS AND DFG RESTRUCTURING
Authors:
Daniel Gomez-Prado, Maciej Ciesielski and Russell Tessier, University of Massachusetts Amherst, US
Abstract
14:4511.2.3A TRANSPARENT AND ENERGY AWARE RECONFIGURABLE MULTIPROCESSOR PLATFORM FOR SIMULTANEOUS ILP AND TLP EXPLOITATION
Authors:
Mateus Rutzig1, Antonio Carlos Schneider Beck2 and Luigi Carro2
1Federal University of Santa Maria, BR; 2Federal University of Rio Grande do Sul, BR
Abstract
15:0011.2.4HIGH-LEVEL MODELING AND SYNTHESIS FOR EMBEDDED FPGAS
Authors:
Xiaolin Chen, Shuai Li, Jochen Schleifer, Thomas Coenen, Anupam Chattopadhyay, Gerd Ascheid and Tobias Noll, RWTH Aachen University, DE
Abstract
15:30IP5-11, 851SCHEDULING INDEPENDENT LIVENESS ANALYSIS FOR REGISTER BINDING IN HIGH LEVEL SYNTHESIS
Authors:
Vito Giovanni Castellana and Fabrizio Ferrandi, Politecnico di Milano, IT
Abstract
15:31IP5-12, 60FAST SHARED ON-CHIP MEMORY ARCHITECTURE FOR EFFICIENT HYBRID COMPUTING WITH CGRAS
Authors:
Jongeun Lee, Yeonghun Jeong and Sungsok Seo, UNIST, KR
Abstract
15:32IP5-13, 59COMPILING CONTROL-INTENSIVE LOOPS FOR CGRAS WITH STATE-BASED FULL PREDICATION
Authors:
Kyuseung Han1, Jongeun Lee2 and Kiyoung Choi1
1Seoul National University, KR; 2UNIST, KR
Abstract
15:30End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

11.3 Efficient NoC Routing Mechanisms

Date: Thursday 21 March 2013
Time: 14:00 - 15:30
Location / Room: Stendahl

Chair:
Fabien Clermidy, CEA-LETI, FR

Co-Chair:
Jose Flich, Technical University of Valencia, ES

This session proposes novel NoC routing mechanisms and policies that push the envelope of efficient SoC design. The first paper reduces latencies in deflection-based systems, while the other two focus on fault tolerance.

TimeLabelPresentation Title
Authors
14:0011.3.1DEBAR: DEFLECTION BASED ADAPTIVE ROUTER WITH MINIMAL BUFFERING
Authors:
John Jose, Bhawna Nayak, Kranthi Kumar and Madhu Mutyam, Indian Institute of Technology Madras, IN
Abstract
14:3011.3.2CONTRASTING WAVELENGTH-ROUTED OPTICAL NOC TOPOLOGIES FOR POWER-EFFICIENT 3D-STACKED MULTICORE PROCESSORS USING PHYSICAL-LAYER ANALYSIS
Authors:
Luca Ramini1, Paolo Grani2, Sandro Bartolini2 and Davide Bertozzi1
1University of Ferrara, IT; 2University of Siena, IT
Abstract
15:0011.3.3TOPOLOGY AGNOSTIC FAULT-TOLERANT NOC ROUTING METHOD
Authors:
Eduardo Wachter, Augusto Erichsen, Alexandre Amory and Fernando Moraes, PUCRS, BR
Abstract
15:30IP5-14, 541FAULT-TOLERANT ROUTING ALGORITHM FOR 3D NOC USING HAMILTONIAN PATH STRATEGY
Authors:
Masoumeh Ebrahimi, Masoud Daneshtalab and Juha Plosila, University of Turku, FI
Abstract
15:31IP5-15, 604MODELING AND ANALYSIS OF FAULT-TOLERANT DISTRIBUTED MEMORIES FOR NETWORKS-ON-CHIP
Authors:
Abbas BanaiyanMofrad1, Gustavo Girão2 and Nikil Dutt1
1University of California, Irvine, US; 2Federal University of Rio Grande do Sul, BR
Abstract
15:30End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

11.4 System-Level Modelling for Physical Properties

Date: Thursday 21 March 2013
Time: 14:00 - 15:30
Location / Room: Chartreuse

Chair:
Frank Oppenheimer, OFFIS, DE

Co-Chair:
François Pêcheux, UPMC, FR

Physical properties have a great impact on the robustness and predictable behaviour of complex micro-electronic systems, and therefore should be considered at system-level. The first paper addresses power and thermal management at the transaction level, while the last two papers present innovative analysis techniques to increase system reliability.

TimeLabelPresentation Title
Authors
14:0011.4.1SYSTEM-LEVEL MODELING OF ENERGY IN TLM FOR EARLY VALIDATION OF POWER AND THERMAL MANAGEMENT
Authors:
Tayeb Bouhadiba1, Matthieu Moy2 and Florence Maraninchi2
1Verimag/CNRS, FR; 2Verimag/Grenoble INP, FR
Abstract
14:3011.4.2SYSTEM-LEVEL MODELING AND MICROPROCESSOR RELIABILITY ANALYSIS FOR BACKEND WEAROUT MECHANISMS
Authors:
Chang-Chih Chen and Linda Milor, Georgia Institute of Technology, US
Abstract
15:0011.4.3AUTOMATIC SUCCESS TREE-BASED RELIABILITY ANALYSIS FOR THE CONSIDERATION OF TRANSIENT AND PERMANENT FAULTS
Authors:
Hananeh Aliee, Michael Glaß, Felix Reimann and Jürgen Teich, University of Erlangen-Nuremberg, DE
Abstract
15:30IP5-16, 574HYBRID PROTOTYPING OF MULTICORE EMBEDDED SYSTEMS
Authors:
Ehsan Saboori and Samar Abdi, Concordia University, CA
Abstract
15:30End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

11.5 Energy Challenges for Multi-Core and NoC Architectures

Date: Thursday 21 March 2013
Time: 14:00 - 15:30
Location / Room: Meije

Chair:
Alberto Garcia-Ortiz, University of Bremen, DE

Co-Chair:
Domenik Helms, OFFIS, DE

This session presents four papers targeting multi-core and NoCs architectures. The first paper presents models for protecting and preventing intermittent device defects. The second paper proposes a self-resetting logic repeater (SRLR) for a signaling datapath of a mesh NoC. The third paper describes how 3D technology can be used to regulate power delivery for a multi-core system. Finally, the fourth paper presents a data-path merging heat distribution aware algorithm for coarse-grained reconfigurable processors.

TimeLabelPresentation Title
Authors
14:0011.5.1COMMUNICATION AND MIGRATION ENERGY AWARE DESIGN SPACE EXPLORATION FOR MULTICORE SYSTEMS WITH INTERMITTENT FAULTS
Authors:
Anup Das, Akash Kumar and Bharadwaj Veeravalli, National University of Singapore, SG
Abstract
14:3011.5.240.4FJ/BIT/MM LOW-SWING ON-CHIP SIGNALING WITH SELF-RESETTING LOGIC REPEATERS EMBEDDED WITHIN A MESH NOC IN 45NM SOI CMOS
Authors:
Sunghyun Park, Masood Qazi, Li-Shiuan Peh and Anantha Chandrakasan, MIT, US
Abstract
15:0011.5.33D RECONFIGURABLE POWER SWITCH NETWORK BY SPACE-TIME MULTIPLEXING FOR DEMAND-SUPPLY MATCHING BETWEEN ON-CHIP MULTI-OUTPUT POWER CONVERTERS AND MANY-CORE MICROPROCESSORS
Authors:
Kanwen Wang1, Hao Yu1, Chun Zhang2 and Benfei Wang1
1Nanyang Technological University, SG; 2Missouri University of Science and Technology, US
Abstract
15:1511.5.4THERMAL-AWARE DATAPATH MERGING FOR COARSE-GRAINED RECONFIGURABLE PROCESSORS
Authors:
Sotirios Xydis, Gianluca Palermo and Cristina Silvano, Politecnico di Milano, IT
Abstract
15:30End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

11.6 Modelling and Design for Signal and Power Integrity

Date: Thursday 21 March 2013
Time: 14:00 - 15:30
Location / Room: Bayard

Chair:
Stefano Grivet-Talocia, Politecnico di Torino, IT

This session discusses state-of-the-art approaches for modelling and design optimization of signal and power distribution networks. Advancements are illustrated on power supply pads placement based on locality and temperature-dependent electromigration, on optimized GPU implementations for capacitance extraction, jitter charaterization via incoherent undersampling and coding-based crosstalk mitigation.

TimeLabelPresentation Title
Authors
14:0011.6.1PLACEMENT OPTIMIZATION OF POWER SUPPLY PADS BASED ON LOCALITY
Authors:
Pingqiang Zhou, Vivek Mishra and Sachin Sapatnekar, University of Minnesota, Twin Cities, US
Abstract
14:3011.6.2GPU-FRIENDLY FLOATING RANDOM WALK ALGORITHM FOR CAPACITANCE EXTRACTION OF VLSI INTERCONNECTS
Authors:
Kuangya Zhai, Wenjian Yu and Hao Zhuang, Tsinghua University, CN
Abstract
15:0011.6.3(Best Paper Award Candidate)
PERIODIC JITTER AND BOUNDED UNCORRELATED JITTER DECOMPOSITION OF INCOHERENT UNDERSAMPLING
Authors:
Nicholas Tzou, Debesh Bhatta, Sen-Wen Hsiao and Abhijit Chatterjee, Georgia Tech, US
Abstract
15:1511.6.4CROSSTALK AVOIDANCE CODES FOR 3D VLSI
Speaker:
Sachin Sapatnekar, University of Minnesota, US
Authors:
Rajeev Kumar and Sunil Khatri, Texas A&M University, US
Abstract
15:30IP5-17, 915LARGE-SCALE FLIP-CHIP POWER GRID REDUCTION WITH GEOMETRIC TEMPLATES
Author:
Zhuo Feng, Michigan Technological University, US
Abstract
15:30End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

11.7 Powerful Aging

Date: Thursday 21 March 2013
Time: 14:00 - 15:30
Location / Room: Les Bans

Chair:
Jose Pineda de Gyvez, NXP Semiconductors, NL

Co-Chair:
Mehdi Tahoori, Karlsruhe Institute of Technology, DE

This session focuses on two general topics: power supply networks and transistor aging effects. The first paper proposes a methodology to more accurately select library characterization voltages to account for aging in the presence of adaptive voltage scaling. The second paper provides an efficient way to simultaneously analyze the electrical and thermal behaviour of a power grid while the third paper uses process, voltage, temperature, and aging sensors at the architecture level to improve the performance of a circuit. The fourth paper describes a new way to construct area-efficient irregular power networks.

TimeLabelPresentation Title
Authors
14:0011.7.1(Best Paper Award Candidate)
IMPACT OF ADAPTIVE VOLTAGE SCALING ON AGING-AWARE SIGNOFF
Authors:
Tuck-Boon Chan, Wei-Ting Chan and Andrew B. Kahng, University of California, San Diego, US
Abstract
14:3011.7.2A PARALLEL FAST TRANSFORM-BASED PRECONDITIONING APPROACH FOR ELECTRICAL-THERMAL CO-SIMULATION OF POWER DELIVERY NETWORKS
Authors:
Konstantis Daloukas, Alexia Marnari, Nestor Evmorfopoulos, Panagiota Tsompanopoulou and George I. Stamoulis, University of Thessaly, GR
Abstract
15:0011.7.3HIERARCHICALLY FOCUSED GUARDBANDING: AN ADAPTIVE APPROACH TO MITIGATE PVT VARIATIONS AND AGING
Authors:
Abbas Rahimi1, Luca Benini2 and Rajesh Gupta1
1University of California, San Diego, US; 2University of Bologna, IT
Abstract
15:1511.7.4EFFECTIVE POWER NETWORK PROTOTYPING VIA STATISTICAL-BASED CLUSTERING AND SEQUENTIAL LINEAR PROGRAMMING
Authors:
Sean Shih-Ying Liu1, Chieh-Jui Lee1, Chuan-Chia Huang1, Hung-Ming Chen1, Chang-Tzu Lin2 and Chia-Hsin Lee2
1National Chiao Tung University, TW; 2Industrial Technology Research Institute, TW
Abstract
15:30IP5-18, 581A NETWORK-FLOW BASED ALGORITHM FOR POWER DENSITY MITIGATION AT POST-PLACEMENT STAGE
Authors:
Sean Shih-Ying Liu, Ren-Guo Luo and Hung-Ming Chen, National Chiao Tung University, TW
Abstract
15:31IP5-19, 858AN EFFICIENT WIRELENGTH MODEL FOR ANALYTICAL PLACEMENT
Authors:
B.N.B. Ray and Shankar Balachandran, Indian Institute of Technology Madras, IN
Abstract
15:30End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

11.8 EMBEDDED TUTORIAL: Advances in Asynchronous Logic: from Principles to GALS & NoC, Recent Industry Applications, and Commercial CAD Tools

Date: Thursday 21 March 2013
Time: 14:00 - 15:30
Location / Room: Lesdigiueres (Exhibition Theatre)

Organiser:
Pascal Vivet, CEA-LETI, FR

Chair:
Robin Wilson, STMicroelectronics, FR

Co-Chair:
Beigné Edith, CEA-LETI, FR

The growing variability and complexity of advanced CMOS technologies makes the physical design of clocked logic in large Systems-on-Chip more and more challenging. Asynchronous logic has been studied for many years and become an attractive solution for a broad range of applications, from massively parallel multi-media systems to systems with ultra-low power & low-noise constraints, like cryptography, energy autonomous systems, and sensor-network nodes. The objective of this embedded tutorial is to give a comprehensive and recent overview of asynchronous logic. The tutorial will cover the basic principles and advantages of asynchronous logic, some insights on new research challenges, and will present the GALS scheme as an intermediate design style with recent results in asynchronous Network-on-Chip for future Many Core architectures. Regarding industrial acceptance, recent asynchronous logic applications within the microelectronics industry will be presented, with a main focus on the commercial CAD tools available today.

TimeLabelPresentation Title
Authors
14:0011.8.1ASYNCHRONOUS DESIGN PRINCIPLES, FROM INTRODUCTION TO RESEARCH CHALLENGES
Author:
Alex Yakovlev, Newcastle University, UK
Abstract
14:3011.8.2GALS & NOC FOR STRUCTURED SOC LEVEL INTERCONNECTS, AND ADVANCES OF ASYNCHRONOUS LOGIC IN THE INDUSTRY
Author:
Pascal Vivet, CEA-Leti, FR
Abstract
15:0011.8.3INTRODUCTION TO TIEMPO ASYNCHRONOUS CIRCUIT SYNTHESIS AND DESIGN FLOW
Author:
Marc Renaudin, TIEMPO, FR
Abstract
15:30End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.

UB11 Session 11

Date: Thursday 21 March 2013
Time: 14:00 - 16:00
Location / Room: Booth 46, Exhibition

TimeLabelPresentation Title
Authors
14:00UB11.1AUDIO SIGNAL RECONSTRUCTION FROM A DAMAGED COCHLEA MODEL
Authors:
Umberto Cerasani1 and William Tatinian2
1LEAT, FR; 2UNICE, FR
Abstract
14:00UB11.2SYNTHORUS-2: AUTOMATIC PROTOTYPING ON FPGA FROM PSL
Authors:
Fatemeh Javaheri, Katell Morin‐Allory, Alexandre Porcher and Dominique Borrione, TIMA Lab, FR
Abstract
14:00UB11.3EMBEDDED GREEN SYSTEM PROJECT: POWER MANAGEMENT TECHNIQUES FOR THE HARVESTED ENERGY BASED SYSTEM
Authors:
Kyungsoo Lee and Tohru Ishihara, Kyoto University, JP
Abstract
14:00UB11.5SIMULINK-BASED HIGH LEVEL HARDWARE SYNTHESIS AND DESIGN SPACE EXPLORATION
Authors:
Shahzad Ahmad Butt and Luciano Lavagno, Politecnico di Torino, IT
Abstract
14:00UB11.6BUILT-IN P/N SELF-ADJUSTMENT: POST-SILICON P/N-PERFORMANCE COMPENSATION SCHEME COMPATIBLE WITH CELL-BASED DESIGN
Authors:
A.K.M. Mahfuzul Islam, Norihiro Kamae, Tohru Ishihara and Hidetoshi Onodera, Kyoto University, JP
Abstract
14:00UB11.7A COMPLETE SUITE OF OPEN/FREE EDA TOOLS FOR PE PHYSICAL DESIGN
Authors:
Francesc Vila1, Jofre Pallarès1, Lluis Terés2, Jordi Carrabina3 and Keith Sabine4
1ICAS, IMB-CNM (CSIC), ES; 2ICAS, IMB-CNM (CSIC) and CAIAC, Universitat Autònoma de Barcelona, ES; 3CAIAC, Universitat Autònoma de Barcelona, ES; 4Peardrop design, ES
Abstract
14:00UB11.8ASAM TOOLS DEMONSTRATION
Authors:
Felipe Chies1, Rosilde Corvino2, Erkan Diken2, Christof Douma3, Agostino Galluzzo4, Deepak Gangadharan5, Roel Jordans2, Lech Jozwiak2, Bart Kienhuis6, Menno Lindwer1, Jan Madsen5, Paolo Meloni7, Laura Micconi5, Giuseppe Notarangelo4, Sebastiano Pomata7, Luigi Raffo7 and Giuseppe Tuveri7
1Intel, NL; 2Eindhoven University of Technology, NL; 3ACE, NL; 4ST, IT; 5DTU, DK; 6Compaan, NL; 7UNICA, IT
Abstract
14:00UB11.9PONG: APPLICATION FOR TEACHING CHIP DESIGN
Authors:
Armin Gruenewald, Matthias Mielke and Rainer Brück, University of Siegen, DE
Abstract
16:00End of session

IP5 Interactive Presentations

Date: Thursday 21 March 2013
Time: 15:30 - 16:00
Location / Room: Exhibition Hall (espace accueil)

Interactive Presentations run simulatenously during a 30-minute slot. A poster associated to the IP paper is on display throughout the afternoon. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session, prior to the actual Interactive Presentation.

LabelPresentation Title
Authors
IP5-1MITIGATING DARK SILICON PROBLEMS USING SUPERLATTICE-BASED THERMOELECTRIC COOLERS
Authors:
Francesco Paterna and Sherief Reda, Brown University, US
Abstract
IP5-2RUN-TIME PROBABILISTIC DETECTION OF MISCALIBRATED THERMAL SENSORS IN MANY-CORE SYSTEMS
Authors:
Jia Zhao, Shiting (Justin) Lu, Wayne Burleson and Russell Tessier, University of Massachusetts Amherst, US
Abstract
IP5-3FORMAL ANALYSIS OF STEADY STATE ERRORS IN FEEDBACK CONTROL SYSTEMS USING HOL-LIGHT
Authors:
Osman Hasan and Muhammad Ahmad, National University of Sciences and Technology, PK
Abstract
IP5-4A NOVEL CONCURRENT CACHE-FRIENDLY BINARY DECISION DIAGRAM CONSTRUCTION FOR MULTI-CORE PLATFORMS
Authors:
Mahmoud El-Bayoumi1, Michael Hsiao1 and Mustafa ElNainay2
1Virginia Tech, US; 2Alexanderia University, EG
Abstract
IP5-5STATISTICAL MODELING WITH THE VIRTUAL SOURCE MOSFET MODEL
Authors:
Li Yu1, Lan Wei1, Dimitri Antoniadis1, Ibrahim Elfadel2 and Duane Boning1
1Massachusetts Institute of Technology, US; 2Masdar Institute of Science and Technology, AE
Abstract
IP5-6AUTOMATIC CIRCUIT SIZING TECHNIQUE FOR THE ANALOG CIRCUITS WITH FLEXIBLE TFTS CONSIDERING PROCESS VARIATION AND BENDING EFFECTS
Authors:
Yen-Lung Chen, Wan-Rong Wu, Guan-Ruei Lu and Chien-Nan Jimmy Liu, National Central University, TW
Abstract
IP5-7AN ENHANCED DOUBLE-TSV SCHEME FOR DEFECT TOLERANCE IN 3D-IC
Authors:
Hsiu-Chuan Shih and Cheng-Wen Wu, National Tsing Hua University, TW
Abstract
IP5-8MEMPACK: AN ORDER OF MAGNITUDE REDUCTION IN THE COST, RISK, AND TIME FOR MEMORY COMPILER CERTIFICATION
Authors:
Kartik Mohanram1, Matthew Wartell1 and Sundar Iyer2
1University of Pittsburgh, US; 2Memoir Systems, US
Abstract
IP5-9EXPLOITING REPLICATED CHECKPOINTS FOR SOFT ERROR DETECTION AND CORRECTION
Authors:
Fahrettin Koc, Kenan Bozdas, Burak Karsli and Oguz Ergin, TOBB University of Economics and Technology, TR
Abstract
IP5-10AN INTEGRATED APPROACH FOR MANAGING THE LIFETIME OF FLASH-BASED SSDS
Authors:
Sungjin Lee, Taejin Kim, Ji-Sung Park and Jihong Kim, Seoul National University, KR
Abstract
IP5-11SCHEDULING INDEPENDENT LIVENESS ANALYSIS FOR REGISTER BINDING IN HIGH LEVEL SYNTHESIS
Authors:
Vito Giovanni Castellana and Fabrizio Ferrandi, Politecnico di Milano, IT
Abstract
IP5-12FAST SHARED ON-CHIP MEMORY ARCHITECTURE FOR EFFICIENT HYBRID COMPUTING WITH CGRAS
Authors:
Jongeun Lee, Yeonghun Jeong and Sungsok Seo, UNIST, KR
Abstract
IP5-13COMPILING CONTROL-INTENSIVE LOOPS FOR CGRAS WITH STATE-BASED FULL PREDICATION
Authors:
Kyuseung Han1, Jongeun Lee2 and Kiyoung Choi1
1Seoul National University, KR; 2UNIST, KR
Abstract
IP5-14FAULT-TOLERANT ROUTING ALGORITHM FOR 3D NOC USING HAMILTONIAN PATH STRATEGY
Authors:
Masoumeh Ebrahimi, Masoud Daneshtalab and Juha Plosila, University of Turku, FI
Abstract
IP5-15MODELING AND ANALYSIS OF FAULT-TOLERANT DISTRIBUTED MEMORIES FOR NETWORKS-ON-CHIP
Authors:
Abbas BanaiyanMofrad1, Gustavo Girão2 and Nikil Dutt1
1University of California, Irvine, US; 2Federal University of Rio Grande do Sul, BR
Abstract
IP5-16HYBRID PROTOTYPING OF MULTICORE EMBEDDED SYSTEMS
Authors:
Ehsan Saboori and Samar Abdi, Concordia University, CA
Abstract
IP5-17LARGE-SCALE FLIP-CHIP POWER GRID REDUCTION WITH GEOMETRIC TEMPLATES
Author:
Zhuo Feng, Michigan Technological University, US
Abstract
IP5-18A NETWORK-FLOW BASED ALGORITHM FOR POWER DENSITY MITIGATION AT POST-PLACEMENT STAGE
Authors:
Sean Shih-Ying Liu, Ren-Guo Luo and Hung-Ming Chen, National Chiao Tung University, TW
Abstract
IP5-19AN EFFICIENT WIRELENGTH MODEL FOR ANALYTICAL PLACEMENT
Authors:
B.N.B. Ray and Shankar Balachandran, Indian Institute of Technology Madras, IN
Abstract

12.1 SPECIAL DAY on "Electronic Technologies for Smart Cities" - HOT TOPIC: Internet of Energy - Connecting Smart Mobility in the Cloud

Date: Thursday 21 March 2013
Time: 16:00 - 17:30
Location / Room: Oisans

Organiser:
Ovidiu Vermesan, SINTEF, NO

Chair:
Andrea Acquavivia, Politecnico di Torino, IT

Co-Chair:
Marcello Coppola, STMicroelectronics, FR

The Internet of Energy (IoE) provides an innovative concept for power distribution, energy storage, grid monitoring and communication. It will allow units of energy to be transferred when and where it is needed. Power consumption monitoring will be performed on all levels, from local individual devices up to national and international level. In this context the new smart electric mobility vehicles will be integrated in the Internet of Energy, creating new mobile ecosystems based on trust, security and convenience to mobile/contactless services and transportation applications will ensure security, mobility and convenience to consumer-centric transactions and services. This special session/workshop will provide different views on the smart mobility concepts and future electric mobility trends by addressing the interaction with the smart city environments in creating an intelligent energy network platform for sustainable transportation systems.

TimeLabelPresentation Title
Authors
16:0012.1.1INTERACTIONS OF LARGE SCALE EV MOBILITY AND VIRTUAL POWER PLANTS
Authors:
Randolf Mock1, Johannes Reinschke1, Tullio Salmon Cinotti2 and Luciano Bononi2
1Siemens, DE; 2University of Bologna, IT
Abstract
16:1512.1.2INNOVATIVE ENERGY STORAGE SOLUTIONS FOR FUTURE ELECTRO MOBILITY IN SMART CITIES
Author:
Kevin Green, Qinetiq, UK
Abstract
16:3012.1.3AUTOMOTIVE ETHERNET: IN-VEHICLE NETWORKING AND SMART MOBILITY
Authors:
Peter Hank, Thomas Suermann and Steffen Müller, NXP Semiconductors, DE
Abstract
16:4512.1.4SMART, CONNECTED AND MOBILE: ARCHITECTING FUTURE ELECTRIC MOBILITY ECOSYSTEMS
Authors:
Ovidiu Vermesan1, Lars-Cyril Blystad1, Reiner John2, Peter Hank3, Roy Bahr1 and Alessandro Moscatelli4
1SINTEF, NO; 2Infineon Technologies, DE; 3NXP Semiconductors, DE; 4STMicroelectronics, IT
Abstract
17:0012.1.5E-MOBILITY THE NEXT FRONTIER FOR AUTOMOTIVE INDUSTRY
Authors:
Roberto Zafalon1, Giovanni Coppola2 and Ovidiu Vermesan3
1STMicroelectronics, IT; 2Enel distribuzione, IT; 3SINTEF, NO
Abstract
17:1512.1.6SEMICONDUCTOR TECHNOLOGIES FOR SMART MOBILITY MANAGEMENT
Authors:
Reiner John1, Martin Schulz1, Ovidiu Vermesan2 and Kai Kriegel3
1Infineon Technologies, DE; 2SINTEF, NO; 3Siemens, DE
Abstract
17:30End of session

12.2 Methodologies to Improve Yield, Reliability and Security in Embedded Systems

Date: Thursday 21 March 2013
Time: 16:00 - 17:30
Location / Room: Belle-Etoile

Chair:
Luciano Lavagno, Politecnico di Torino, IT

Co-Chair:
Jürgen Teich, University of Erlangen-Nuremberg, DE

The first paper in the session discusses how to selectively duplicate hardware in order to optimize yield in a binning scenario. The second paper also uses duplication and re-execution to optimize software reliability by taking error masking into account. Finally the third paper considers variable levels of security and intrusion detection, while satisfying tight performance constraints both at design and at run-time.

TimeLabelPresentation Title
Authors
16:0012.2.1(Best Paper Award Candidate)
A NEW PARADIGM FOR TRADING OFF YIELD, AREA AND PERFORMANCE TO ENHANCE PERFORMANCE PER WAFER
Authors:
Yue Gao, Melvin Breuer and Yanzhi Wang, University of Southern California, US
Abstract
16:3012.2.2LEVERAGING VARIABLE FUNCTION RESILIENCE FOR SELECTIVE SOFTWARE RELIABILITY ON UNRELIABLE HARDWARE
Authors:
Semeen Rehman, Muhammad Shafique, Pau Vilimelis Aceituno, Florian Kriebel, Jian-Jia Chen and Jörg Henkel, Karlsruhe Institute of Technology, DE
Abstract
17:0012.2.3OPTIMIZATION OF SECURE EMBEDDED SYSTEMS WITH DYNAMIC TASK SETS
Authors:
Ke Jiang, Petru Eles and Zebo Peng, Linköping University, SE
Abstract
17:30End of session

12.3 NoC Mapping and Synthesis

Date: Thursday 21 March 2013
Time: 16:00 - 17:30
Location / Room: Stendahl

Chair:
Andreas Hansson, ARM, UK

Co-Chair:
Jaime Murillo, EPFL, CH

This session optimizes NoC performance by means of design-time algorithms. Two of the papers focus on mapping of applications on NoCs, while the third proposes new means of synthesizing efficient NoC topologies.

TimeLabelPresentation Title
Authors
16:0012.3.1SHARED MEMORY AWARE MPSOC SOFTWARE DEPLOYMENT
Authors:
Timo Schönwald1, Alexander Viehl1, Oliver Bringmann2 and Wolfgang Rosenstiel2
1FZI Forschungszentrum Informatik, DE; 2University of Tuebingen, DE
Abstract
16:3012.3.2FAST AND OPTIMIZED TASK ALLOCATION METHOD FOR LOW VERTICAL LINK DENSITY 3-DIMENSIONAL NETWORKS-ON-CHIP BASED MANY CORE SYSTEMS
Authors:
Haoyuan Ying1, Thomas Hollstein2 and Klaus Hofmann1
1Darmstadt University of Technology, DE; 2Tallinn University of Technology, EE
Abstract
17:0012.3.3A SPECTRAL CLUSTERING APPROACH TO APPLICATION-SPECIFIC NETWORK-ON-CHIP SYNTHESIS
Authors:
Vladimir Todorov1, Daniel Mueller-Gritschneder2, Helmut Reinig1 and Ulf Schlichtmann2
1Intel Mobile Communications, DE; 2Technische Universität München, DE
Abstract
17:30End of session

12.4 Emerging Logic

Date: Thursday 21 March 2013
Time: 16:00 - 17:30
Location / Room: Chartreuse

Chair:
Aida Todri-Sanial, CNRS-LIRMM, FR

Co-Chair:
Marco Ottavi, University of Rome "Tor Vegata", IT

This session contains papers on emerging logic including nano-magentic logic, graphene FETs, nano-corssbar arrays, and single-electron transistors.

TimeLabelPresentation Title
Authors
16:0012.4.1A SPICE-COMPATIBLE MODEL OF GRAPHENE NANO-RIBBON FIELD-EFFECT TRANSISTORS ENABLING CIRCUIT-LEVEL DELAY AND POWER ANALYSIS UNDER PROCESS VARIATION
Authors:
Ying-Yu Chen1, Artem Rogachev1, Amit Sangai1, Giuseppe Iannaccone2, Gianluca Fiori2 and Deming Chen1
1University of Illinois at Urbana-Champaign, US; 2University of Pisa, IT
Abstract
16:3012.4.2SYSTEMATIC DESIGN OF NANOMAGNET LOGIC CIRCUITS
Authors:
Indranil Palit, Michael Niemier, Xiaobo Hu and Joshep Nahas, University of Notre Dame, US
Abstract
17:0012.4.3DEFECT-TOLERANT LOGIC HARDENING FOR CROSSBAR-BASED NANOSYSTEMS
Authors:
Yehua Su and Wenjing Rao, University of Illinois at Chicago, US
Abstract
17:1512.4.4ON RECONFIGURABLE SINGLE-ELECTRON TRANSISTOR ARRAYS SYNTHESIS USING REORDERING TECHNIQUES
Authors:
Chang-En Chiang1, Li-Fu Tang1, Chun-Yao Wang1, Ching-Yi Huang1, Yung-Chih Chen2, Suman Datta3 and Vijaykrishnan Narayanan3
1National Tsing Hua University, TW; 2Yuan Ze University, TW; 3Pennsylvania State University, US
Abstract
17:30End of session

12.5 Emerging Technology Architectures for Energy-Efficient Memories

Date: Thursday 21 March 2013
Time: 16:00 - 17:30
Location / Room: Meije

Chair:
Marisa López-Vallejo, Universidad Politecnica Madrid, ES

Co-Chair:
Alberto Macii, Politecnico di Torino, IT

This session presents three papers targeting energy efficiency in memory architectures. The first paper presents a new hybrid DRAM/MRAM approach, the second paper describes a sensitivity analysis to simulate SRAMs dynamic write-ability under process variations and the third one reports how domain wall memories can be used for design on-chip cache hierarchies.

TimeLabelPresentation Title
Authors
16:0012.5.1D-MRAM CACHE: ENHANCING ENERGY EFFICIENCY WITH 3T-1MTJ DRAM / MRAM HYBRID MEMORY
Authors:
Hiroki Noguchi1, Kumiko Nomura1, Keiko Abe1, Shinobu Fujita1, Eishi Arima2, Kyundong Kim2, Takashi Nakada2, Shinobu Miwa2 and Hiroshi Nakamura2
1Toshiba, JP; 2University of Tokyo, JP
Abstract
16:3012.5.2LEVERAGING SENSITIVITY ANALYSIS FOR FAST, ACCURATE ESTIMATION OF SRAM DYNAMIC WRITE VMIN
Authors:
James Boley1, Vikas Chandra2, Rob Aitken2 and Benton Calhoun1
1University of Virginia, US; 2ARM, US
Abstract
17:0012.5.3DWM-TAPESTRI - AN ENERGY EFFICIENT ALL-SPIN CACHE USING DOMAIN WALL SHIFT BASED WRITES
Authors:
Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy and Anand Raghunathan, Purdue University, US
Abstract
17:30End of session

12.6 Clock Distribution and Analogue Circuit Synthesis

Date: Thursday 21 March 2013
Time: 16:00 - 17:30
Location / Room: Bayard

Chair:
Tiziano Villa, University of Verona, IT

Co-Chair:
Georges Gielen, Katholieke Universiteit Leuven, BE

The first two papers of this session address the optimization of clock distribution. The first paper deals with clock-skew scheduling combined with clock-gating. The second paper addresses the power reduction of the clock-tree using multi-bit flip-flops. The last two papers of this session address the synthesis of analogue circuits, dealing with hierarchy, layout issues, and non-CMOS technologies.

TimeLabelPresentation Title
Authors
16:0012.6.1CO-SYNTHESIS OF DATA PATHS AND CLOCK CONTROL PATHS FOR MINIMUM-PERIOD CLOCK GATING
Authors:
Wen-Pin Tu, Shih-Hsu Huang and Chun-Hua Cheng, Chung Yuan Christian University, TW
Abstract
16:3012.6.2SLACK BUDGETING AND SLACK-TO-ENGTH CONVERTING FOR MULTI-BIT FLIP-FLOP MERGING
Authors:
Chia-Chieh Lu and Rung-Bin Lin, Yuan Ze University, TW
Abstract
16:4512.6.3AREA OPTIMIZATION ON FIXED ANALOG FLOORPLANS USING CONVEX AREA FUNCTIONS
Authors:
Ahmet Unutulmaz1, Gunhan Dundar1 and Francisco Fernandez2
1Bogazici University, TR; 2IMSE-CNM, CSIC and University of Sevilla, ES
Abstract
17:0012.6.4PAGE: PARALLEL AGILE GENETIC EXPLORATION TOWARD UTMOST PERFORMANCE FOR ANALOG CIRCUIT DESIGN
Authors:
Po-Cheng Pan, Hung-Ming Chen and Chien-Chih Lin, National Chiao Tung University, TW
Abstract
17:30End of session

12.7 Physical Design

Date: Thursday 21 March 2013
Time: 16:00 - 17:30
Location / Room: Les Bans

Chair:
Carl Sechen, University of Texas at Dallas, US

Co-Chair:
Bill Swartz, InternetCAD, US

The first paper proposes solving the Lagrangian dual problem using discrete gate sizes. The second paper describes accurate meta-modelling techniques applicable to IC design. The third paper suggests better wire lengths in placement are obtained using a super-linear weighting factor. The last paper shows the advantages of doing layer assignment before global routing.

TimeLabelPresentation Title
Authors
16:0012.7.1FAST AND EFFICIENT LAGRANGIAN RELAXATION-BASED DISCRETE GATE SIZING
Authors:
Vinicius dos S. Livramento1, Chrystian Guth1, José Luís Güntzel1 and Marcelo O. Johann2
1Federal University of Santa Catarina, BR; 2Federal University of Rio Grande do Sul, BR
Abstract
16:3012.7.2ENHANCED METAMODELING TECHNIQUES FOR HIGH-DIMENSIONAL IC DESIGN ESTIMATION PROBLEMS
Authors:
Andrew B. Kahng, Bill Lin and Siddhartha Nath, University of California, San Diego, US
Abstract
17:0012.7.3SUB-QUADRATIC OBJECTIVES IN QUADRATIC PLACEMENT
Author:
Markus Struzyna, University of Bonn, DE
Abstract
17:1512.7.4CATALYST: PLANNING LAYER DIRECTIVES FOR EFFECTIVE DESIGN CLOSURE
Authors:
Yaoguang Wei1, Zhuo Li2, Cliff Sze2, Shiyan Hu3, Charles J. Alpert2 and Sachin S. Sapatnekar1
1University of Minnesota - Twin Cities, US; 2IBM Research - Austin, US; 3Michigan Technological University, US
Abstract
17:30End of session

12.8 EMBEDDED TUTORIAL: Closed-Loop Control for Power and Thermal Management in Multi-core Processors: Formal Methods and Industrial Practice

Date: Thursday 21 March 2013
Time: 16:00 - 17:30
Location / Room: Lesdigiueres (Exhibition Theatre)

Organiser:
Ibrahim Elfadel, Masdar Institute of Science and Technology, AE

Chair:
Petru Eles, Linköping University, SE

Co-Chair:
Jose Ayala, Complutense University of Madrid, ES

The objective of this embedded tutorial is to bring DATE attendees who are interested in low-power design for MPSoC to the forefront of the latest academic research and industrial practice in the area of closed-loop control of power and temperature in MPSoC. Starting with power capping techniques based on classical control theory, the tutorial will cover the more advanced techniques of optimal control, model predictive control, and adaptive control. Practical issues such as power and thermal proxies, power and thermal sensors, and various actuation techniques will be surveyed. Furthermore, the tutorial will cover recent techniques for pro-active and reactive closed-loop temperature control for 2D and 3D MPSoC, including the handling of emerging inter-tier liquid cooling techniques. It will also address optimal power control techniques in NoC architectures, with particular attention to methods for handling multiple voltage and clock domains under variable workloads. Important emerging problems such as heterogeneity of the computational fabric and scalability of the control methods will also be discussed along with their emerging solutions.

TimeLabelPresentation Title
Authors
16:0012.8.1INTRODUCTION
Author:
Ibrahim Elfadel, Masdar Institute of Science and Technology, AE
Abstract
16:1012.8.2CLOSED-LOOP CONTROL FOR POWER AND THERMAL MANAGEMENT IN MULTI-CORE PROCESSORS
Author:
Radu Marculescu, Carnegie Mellon University, US
Abstract
16:5012.8.3THERMAL-AWARE SYSTEM-LEVEL MODELING AND MANAGEMENT FOR MULTI-PROCESSOR SYSTEMS-ON-CHIP
Author:
David Atienza, EPFL, CH
Abstract
17:30End of session
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