Topic: A5 Secure Systems

Secured systems need a combination of hardware, software and embedded techniques to succeed. Indeed, the weakest link in the security chain determines the overall system security. This topic therefore invites papers on novel technologies and experiences for specific security problems as well as overall design integration methods for secure systems-on-chip and embedded systems. Topics of interest are situated at all design abstraction levels and include novel techniques and architectures for embedded cryptography; modeling, characterization, simulation and associated countermeasures for side-channel, fault and other physical attacks; random numbers generation, embedded secure processors and co-processors, trusted computing, off-chip memories and network-on-chip enciphering and integrity checking, trust establishment and attestation; implementation of security applications; hardware enabled security, including physically unclonable functions, and more.

Chair: Jérôme Quévremont, Thales, FR, Contact

Co-Chair: Patrick Schaumont, Virginia Tech, US, Contact

Members:

• guido [dot] bertonist [dot] com, Contact
• Laurent Fesquet, TIMA - Grenoble Institute of Technology, FR, Contact
• Maire O'Neill, Queen's University Belfast, UK, Contact
• Francesco Regazzoni, Université catholique de Louvain and ALaRI, CH, Contact
• Lionel TORRES, LIRMM - University Montpellier 2, FR, Contact
• ingrid [dot] verbauwhedekuleuven [dot] be, Contact