Topic: D13 Physical Design and Verification

Floorplanning; automatic place and route; module generation; design rule checking and layout characterization; electrical verification; problems in deep sub-micron and high-speed design; interconnect-driven and performance-driven layout; process technology developments; design for manufacturability.

Chair: r [dot] h [dot] j [dot] m [dot] ottentue [dot] nl, Contact

Co-Chair: Azadeh Davoodi, University of Wisconsin - Madison, US, Contact

Members:

• Matthew Guthaus, University of California Santa Cruz, US, Contact
• , Contact
• Jens Lienig, Technical University of Dresden, DE, Contact
• Igor Markov, University of Michigan, US, Contact
• Mustafa Ozdal, Intel, US, Contact
• Sven Peyer, IBM, DE, Contact
• Sherief Reda, Brown University, US, Contact
• tcwangcs [dot] nthu [dot] edu [dot] tw, Contact