De-RISC: A Complete RISC-V Based Space-Grade Platform
Nils-Johan Wessman1, Fabio Malatesta1, Stefano Ribes1, Jan Andersson1, Antonio García-Vilanova2, Miguel Masmano2, Vicente Nicolau2, Paco Gomez2, Jimmy Le Rhun3, Sergi Alcaide4, Guillem Cabo4, Francisco Bas4,5, Pedro Benedicte4, Fabio Mazzocchetti4 and Jaume Abella4
1CAES Gaisler, Sweden
2fentISS, Spain
3Thales Research and Technology, France
4Barcelona Supercomputing Center (BSC), Spain
5Universitat Politecnica de Catalunya (UPC), Spain
ABSTRACT
The H2022 EIC-FTI De-RISC project develops a RISC-V space-grade platform to jointly respond to several emerging, as well as longstanding needs in the space domain such as: (1) higher performance than that of monocore and basic multicore space-grade processors in the market; (2) access to an increasingly rich software ecosystem rather than sticking to the slowly fading SPARC and PowerPC-based ones; (3) freedom (or drastic reduction) of export and license restrictions imposed by commercial ISAs such as Arm; and (4) improved support for the design and validation of safetyrelated real-time applications, (5) being the platform with software qualified and hardware designed per established space industry standards.
De-RISC partners have set up the different layers of the platform during the first phases of the project. However, they have recently boosted integration and assessment activities. This paper introduces the De-RISC space platform, presents recent progress such as enabling virtualization and software qualification, new MPSoC features, and use case deployment and evaluation, including a comparison against other commercial platforms. Finally, this paper introduces the ongoing activities that will lead to the hardware and fully qualified software platform at TRL8 on FPGA by September 2022.
