Physical and Functional Reverse Engineering Challenges for Advanced Semiconductor Solutions
Bernhard Lippmann1,a, Ann-Christin Bette1,b, Matthias Ludwig1,2,c, Johannes Mutter1,d, Johanna Baehr2,e, Alexander Hepp2,f, Horst Gieser3,g, Nicola Kovač3,h, Tobias Zweifel3,i, Martin Rasche4,j and Oliver Kellermann4,k
1Infineon Technologies AG, Munich, Germany
abernhard.lippmann@infineon.com
bann-christin.bette@infineon.com
cmatthias.ludwig@infineon.com
djohannes.mutter@infineon.com
2Technical University of Munich, Department of Electrical and Computer Engineering, Munich, Germany
ejohanna.baehr@tum.de
falex.hepp@tum.de
3Fraunhofer EMFT, Munich, Germany
ghorst.gieser@emft.fraunhofer.de
hnicola.kovac@emft.fraunhofer.de
itobias.zweifel@emft.fraunhofer.de
4Raith GmbH, Dortmund, Germany
jmartin.rasche@raith.de
koliver.kellermann@raith.de
ABSTRACT
Motivated by the threats of malicious modification and piracy arising from worldwide distributed supply chains, the goal of RESEC is the creation, verification, and optimization of a complete reverse engineering process for integrated circuits manufactured in technology nodes of 40nm and below. Building upon the presentation of individual reverse engineering process stages, this paper connects analysis efforts and yields with their impact on hardware security, demonstrated on a design with implemented experimental hardware Trojans. We outline the interim stage of our research activities and present our future targets linking chip design and physical verification processes.
Keywords: Hardware Reverse Engineering, Layout Extraction, SEM Imaging, Image Processing, RISC-V, Hardware Trojans.
