Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs
Tim Hotfilter1,a, Fabian Kreß1,b, Fabian Kempf1,c, Jürgen Becker1,d, Juan Miguel de Haro2,e, Daniel Jiménez-González2,f, Miquel Moretó2,g, Carlos Álvarez2,h, Jesús Labarta2,i and Imen Baili3
1Karlsruhe Institute of Technology (KIT)
ahotfilter@kit.edu
bfabian.kress@kit.edu
cfabian.kempf@kit.edu
dbecker@kit.edu
2Barcelona Supercomputing Center (BSC) Universistat Politècnica de Catalunya (UPC)
ejuan.deharoruiz@bsc.es
fdjimenez@bsc.es
gmiquel.moreto@bsc.es
hcarlos.alvarez@bsc.es
ijesus.labarta@bsc.es
3Menta S.A.S
imen.baili@menta-efpga.com
ABSTRACT
The goal of modern high performance computing platforms is to combine low power consumption and high throughput. Within the European Processor Initiative (EPI), such an SoC platform to meet the novel exascale requirements is built and investigated. As part of this project, we introduce an embedded Field Programmable Gate Array (eFPGA), adding flexibility to accelerate various workloads. In this article, we show our approach to design the eFPGA tile that supports the EPI SoC. While eFPGAs are inherently reconfigurable, their initial design has to be determined for tape-out. The design space of the eFPGA is explored and evaluated with different configurations of two HPC workloads, covering control and dataflow heavy applications. As a result, we present a well-balanced eFPGA design that can host several use cases and potential future ones by allocating 1% of the total EPI SoC area. Finally, our simulation results of the architectures on the eFPGA show great performance improvements over their software counterparts.
Keywords: FPGA, HPC, Design space exploration, SoC.
