Physically and Algorithmically Secure Logic Locking with Hybrid CMOS/Nanomagnet Logic Circuits
Alexander J. Edwards1,a, Naimul Hassan1, Dhritiman Bhattacharya2, Mustafa M. Shihab1, Peng Zhou1, Xuan Hu1, Jayasimha Atulasimha2, Yiorgos Makris1 and Joseph S. Friedman1,b
1Department of Electrical and Computer Engineering, University of Texas at Dallas, Richardson, TX 75080
aalexander.edwards@utdallas.edu
bjoseph.friedman@utdallas.edu
2Department of Mechanical and Nuclear Engineering, Virginia Commonwealth University, Richmond, VA 23284
ABSTRACT
The successful logic locking of integrated circuits requires that the system be secure against both algorithmic and physical attacks. In order to provide resilience against imaging techniques that can detect electrical behavior, we recently proposed an approach for physically and algorithmically secure logic locking with strain-protected nanomagnet logic (NML). While this NML system exhibits physical and algorithmic security, the fabrication imprecision, noise-related errors, and slow speed of NML incur a significant security overhead cost. In this paper, we therefore propose a hybrid CMOS/NML logic locking solution in which NML islands provide security within a system primarily composed of CMOS, thereby providing physical and algorithmic security with minimal overhead. In addition to describing this proposed system, we also develop a framework for device/system co-design techniques that consider trade-offs regarding the efficiency and security.
