A Flash-based Current-mode IC to Realize Quantized Neural Networks
Kyler R. Scott1,a, Cheng-Yen Lee1,b, Sunil P. Khatri1,c and Sarma Vrudhula2
1Department of ECE Texas A&M University College Station, USA
akylerrscott@tamu.edu
bcylee@tamu.edu
csunilkhatri@tamu.edu
2Department of ECE Arizona State University Tuscon, USA
vrudhula@asu.edu
ABSTRACT
This paper presents a mixed-signal architecture for implementing Quantized Neural Networks (QNNs) using flash transistors to achieve extremely high throughput with extremely low power, energy and memory requirements. Its low resource consumption makes our design especially suited for use in edge devices. The network weights are stored in-memory using flash transistors, and nodes perform operations in the analog current domain. Our design can be programmed with any QNN whose hyperparameters (the number of layers, filters, or filter size, etc) do not exceed the maximum provisioned. Once the flash devices are programmed with a trained model and the IC is given an input, our architecture performs inference with zero access to offchip memory. We demonstrate the robustness of our design under current-mode non-linearities arising from process and voltage variations. We test validation accuracy on the ImageNet dataset, and show that our IC suffers only 0.6% and 1.0% reduction in classification accuracy for Top-1 and Top-5 outputs, respectively. Our implementation results in a ∼50× reduction in latency and energy when compared to a recently published mixed-signal ASIC implementation, with similar power characteristics. Our approach provides layer partitioning and node sharing possibilities, which allow us to trade off latency, power, and area amongst each other.
Keywords: Quantized Neural Networks, Floating-gate Transistors, Current-mode Circuits.
