Cache-aware Schedulability Analysis of PREM Compliant Tasks
Syed Aftab Rashid1,4, Muhammad Ali Awan1,2, Pedro F. Souto3,1, Konstantinos Bletsas1,2 and Eduardo Tovar1,2
1CISTER Research Centre, Porto, Portugal
2ISEP, Polytechnic Institute of Porto, Portugal
3University of Porto, FEUP-Faculty of Engineering, Porto, Portugal
4VORTEX CoLab, Porto, Portugal
ABSTRACT
The Predictable Execution Model (PREM) is useful for mitigating inter-core interference due to shared resources such as the main memory. However, it is cache-agnostic, which makes schedulabulity analysis pessimistic, via overestimation of prefetches and write-backs. In response, we present cache-aware schedulability analysis for PREM tasks on fixed-task-priority partitioned multicores, that bounds the number of cache prefetches and write-backs. Our approach identifies memory blocks loaded in the execution of a previous scheduling interval of each task, that remain in the cache until its next scheduling interval. Doing so, greatly reduces the estimated prefetches and write backs. In experimental evaluations, our analysis improves the schedulability of PREM tasks by up to 55 percentage points.
