Accelerate Hardware Logging for Efficient Crash Consistency in Persistent Memory
Zhiyuan Lu1,a, Jianhui Yue1,b, Yifu Deng1,c and Yifeng Zhu2
1Computer Science, Michigan Technological University, Houghton, Michigan, USA
azhlu@mtu.edu
bjyue@mtu.edu
cyifud@mtu.edu
2Electrical & Computer Engineering, University of Maine, Orono, Maine, USA
yifeng.zhu@maine.edu
ABSTRACT
While logging has been adopted in persistent memory (PM) to support crash consistency, logging incurs severe performance overhead. This paper discovers two common factors that contribute to the inefficiency of logging: (1) load imbalance among memory banks, and (2) constraints of intra-record ordering. Overloaded memory banks may significantly prolong the waiting time of log requests targeting these banks. To address this issue, we propose a novel log entry allocation scheme (LALEA) that reshapes the traffic distribution over PM banks. In addition, the intra-record ordering between a header and its log entries decreases the degree of parallelism in log operations. We design a log metadata buffering scheme (BLOM) that eliminates the intrarecord ordering constraints. These two proposed log optimizations are general and can be applied to many existing designs. We evaluate our designs using both micro-benchmarks and real PM applications. Our experimental results show that LALEA and BLOM can achieve 54.04% and 17.16% higher transaction throughput on average, compared to two state-of-the-art designs, respectively.
Keywords: Persistent Memory, Crash Consistency, Logging, ADR.
