AID: Accuracy Improvement of Analog Discharge-Based in-SRAM Multiplication Accelerator
Saeed Seyedfarajia, Baset Mesgarib and Semeen Rehmanc
Vienna University of Technology (TU-Wien), Vienna, Austria
asaeed.seyedfaraji@tuwien.ac.at
bbaset.mesgari@tuwien.ac.at
csemeen.rehman@tuwien.ac.at
ABSTRACT
This paper presents a novel circuit (AID) to improve the accuracy of an energy-efficient in-memory multiplier using a standard 6T-SRAM. The state-of-the-art discharge-based in-SRAM multiplication accelerators suffer from a non-linear behavior in their bit-line (BL, BLB) due to the quadratic nature of the access transistor that leads to a poor signal-to-noise ratio (SNR). In order to achieve linearity in the BLB voltage, we propose a novel root function technique on the access transistor's gate that results in accuracy improvement of on average 10.77 dB SNR compared to state-of-the-art discharge-based topologies. Our analytical methods and a circuit simulation in a 65 nm CMOS technology verify that the proposed technique consumes 0.523 pJ per computation (multiplication, accumulation, and preset) from a power supply of 1V, which is 51.18% lower compared to other state-of-the-art techniques. We have performed an extensive Monte Carlo based simulation for a 4x4 multiplication operation, and our novel technique presents less than 0.086 standard deviations for the worstcase incorrect output scenario.
Keywords: Process in Memory, SRAM, Neural Network, Low Power.
