Achieving Crash Consistency by Employing Persistent L1 Cache
Akshay Krishna Ramanathan1,a, Sara Mahdizadeh Shahri2, Yi Xiao1,b and Vijaykrishnan Narayanan1,c
1The Pennsylvania State University
aaxr499@psu.edu
bymx5148@psu.edu
cvxn9@psu.edu
2University of Michigan
smahdiz@umich.edu
ABSTRACT
Emerging non-volatile memory technologies promise the opportunity for maintaining persistent data in memory. However, providing crash-consistency in such systems can be costly as any update to the persistent data has to reach the persistent domain in a specific order, imposing high overhead. Prior works, proposed solutions both in software (SW) and hardware (HW) to address this problem but fall short to remove this overhead completely. In this work, we propose Non-Volatile Cache (NVC) architecture design that employs a hybrid volatile, non-volatile memory cell employing monolithic 3D and Ferroelectric technology in L1 data cache to guarantee crash consistency with almost no performance overhead. We show that NVC achieves up to 5.1x speedup over state-of-the-art (SOTA) SW undo logging and 11% improvement over SOTA HW solution without yielding the conventional architecture, while incurring 7% hardware overhead.
Keywords: Non-Volatile Cache, Persistent Applications, Monolithic-3d Integration, Sram, Ferro-Electric FET.
