Improving Cell-Aware Test for Intra-Cell Short Defects
Dong-Zhen Lee1,2, Ying-Yen Chen1, Kai-Chiang Wu3 and Mango C.-T. Chao2
1Realtek Semiconductor Corporation, Taiwan
2Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
3Department of Computer Science, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
ABSTRACT
Conventional fault models define their faulty behavior at the IO ports of standard cells with simple rules of fault activation and fault propagation. However, there still exist some defects inside a cell (intra-cell) that cannot be effectively detected by the test patterns of conventional fault models and hence become a source of DPPM. In order to further increase the defect coverage, many research works have been conducted to study the fault models resulting from different types of intracell defects, by SPICE-simulating each targeted defect with its equivalent circuit-level defect model. In this paper, we propose to improve cell-aware (CA) test methodology by concentrating on intra-cell bridging faults due to short defects inside standard cells. The faults extracted are based on examining the actual physical proximity of polygons in the layout of a cell, and are thus more realistic and reasonable than those (faults) determined by RC extraction. Experimental results on a set of industrial designs show that the proposed methodology can indeed improve the test quality of intra-cell bridging faults. On average, 0.36% and 0.47% increases in fault coverage can be obtained for 1-timeframe and 2-time-frame CA tests, respectively. In addition to short defects between two metal polygons, short defects among three metal polygons are also considered in our methodology for another 9.33% improvement in fault coverage.
