Space and Power Reduction in BDD-based Optical Logic Circuits Exploiting Dual Ports
Ryosuke Matsuoa and Shin-ichi Minatob
Kyoto University Kyoto, Japan
amatsuo.ryosuke.25r@st.kyoto-u.ac.jp
bminato@i.kyoto-u.ac.jp
ABSTRACT
Optical logic circuits based on integrated nanophotonics have attracted significant interest due to their ultra-highspeed operation. A synthesis method based on the Binary Decision Diagram (BDD) has been studied, as BDD-based optical logic circuits can take advantage of the speed of light. However, a fundamental disadvantage of BDD-based optical logic circuits is a large number of splitters, which results in large power consumption. In BDD-based circuits a dual port of each logic gate is not used. We propose a method for eliminating a splitter exploiting this dual port. We define a BDD node corresponding to a dual port as a dual port node (DP node) and call the proposed method DP node sharing. We demonstrated that DP node sharing significantly reduces the power consumption and to a lesser extent circuit size without increasing delay. We conducted an experiment involving 10-input logic functions obtained by applying an LUT technology mapper to an ISCSA’85 C7552 benchmark circuit to evaluate our DP node sharing. The experimental results demonstrated that DP node sharing reduces the power consumption by two orders of magnitude of circuit that consume a large amount of power.
Keywords: Binary Decision Diagram, Optical Logic circuit, Logic Synthesis.
