Reliability Analysis of a Spiking Neural Network Hardware Accelerator
Theofilos Spyrou1, Sarah A. El-Sayed1, Engin Afacan1, Luis A. Camuñas-Mesa2, Bernabé Linares-Barranco2 and Haralampos-G. Stratigopoulos1
1Sorbonne Université, CNRS, LIP6, Paris, France
2Instituto de Microelectrónica de Sevilla (IMSE-CNM), CSIC y Universidad de Sevilla, Sevilla, Spain
ABSTRACT
Despite the parallelism and sparsity in neural network models, their transfer into hardware unavoidably makes them susceptible to hardware-level faults. Hardware-level faults can occur either during manufacturing, such as physical defects and process-induced variations, or in the field due to environmental factors and aging. The performance under fault scenarios needs to be assessed so as to develop cost-effective fault-tolerance schemes. In this work, we assess the resilience characteristics of a hardware accelerator for Spiking Neural Networks (SNNs) designed in VHDL and implemented on an FPGA. The fault injection experiments pinpoint the parts of the design that need to be protected against faults, as well as the parts that are inherently fault-tolerant.
