SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments
Aibin Yan1, Zhixing Li1, Shiwei Huang1, Zijie Zhai1, Xiangyu Cheng1, Jie Cui1, Tianming Ni2, Xiaoqing Wen3 and Patrick Girard4
1School of Computer Science and Technology, Anhui University, Hefei, China
2College of Electrical Engineering, Anhui Polytechnic University, Wuhu, China
3Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology, Fukuoka, Japan
4LIRMM, University of Montpellier / CNRS, Montpellier, France
ABSTRACT
As the CMOS technology is continuously scaling down, nano-scale integrated circuits are becoming susceptible to harsh-radiation induced soft errors, such as double-node upsets (DNUs) and triple-node upsets (TNUs). This paper presents a shuttle C-elements based low-cost and robust latch (namely SCLCRL) that can recover from any TNU in harsh radiation environments. The latch comprises seven primary storage nodes and seven secondary storage nodes. Each pair of primary nodes feeds a secondary node through one C-element (CE) and each pair of secondary nodes feeds a primary node through another CE, forming redundant feedback loops to robustly retain values. Simulation results validate all key TNUs’ recoverability features of the proposed latch. Simulation results also demonstrate that the proposed SCLCRL latch can approximately save 29% silicon area and 47% D-Q delay on average at the cost of moderate power, compared with the state-of-the-art TNU-recoverable reference latches of the same-type.
