Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays
Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary,
Meghna Madhusudan, Ramesh Harjani, and Sachin S. Sapatnekar
University of Minnesota, Minneapolis, MN, USA
ABSTRACT
The accuracy and linearity of capacitive digital-toanalog converters (DACs) depend on precise capacitor ratios, but these ratios are perturbed by process variations and parasitics. This paper develops fast constructive procedures for commoncentroid placement and routing for binary-weighted capacitors in charge-sharing DACs. Parasitics also degrade the switching speed of a capacitor array, particularly in FinFET nodes with severe wire/via resistances. To overcome this, the capacitor array is placed and routed to optimize switching speed, measured by the 3dB frequency. A balance between 3dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.
