RF-CGRA: A Routing-Friendly CGRA with Hierarchical Register Chains
Rong Zhua, Bo Wangb and Dajiang Liuc
College of Computer Science, Chongqing University, Chongqing 400044, China
azhur@cqu.edu.cn
bwangbocs@cqu.edu.cn
cliudj@cqu.edu.cn
ABSTRACT
CGRAs are promising architectures to accelerate domain-specific applications as they combine high energyefficiency and flexibility. With either isolated register files (RFs) or link-consuming distributed registers in each processing element (PE), existing CGRAs are all not friendly to data routing for data-flow graphs (DFGs) with a high edge/node ratio since there are many multi-cycle dependences. To this end, this paper proposes a Routing-Friendly CGRA (RF-CGRA) where hierarchical (intra-PE or inter-PE) register chains could be flexibly (wide range of chain length) and compactly (consuming fewer links among PEs) achieved for data routing, resulting in a new mapping problem that requires the improvement of a compiler. Experimental results show that RF-CGRA gets 1.19× performance and 1.14× energy efficiency of the state-of-the-art CGRA with single-cycle multi-hop connections (HyCUBE) while keeping a moderate compilation time.
Keywords: CGRAs, Modulo Scheduling, Data Routing.
