Self-Terminating Write of Multi-Level Cell ReRAM for Efficient Neuromorphic Computing
Zongwu Wang1, Zhezhi He1, Rui Yang1, Shiquan Fan2, Jie Lin3, Fangxin Liu1,4, Yueyang Jia1, Chenxi Yuan2, Qidong Tang1 and Li Jiang1,4,5
1Shanghai Jiao Tong University
2Xi’an Jiao Tong University
3University of Central Florida
4Shanghai Qi Zhi Institute
5MoE Key Lab of Artificial Intelligence, AI Institute, Shanghai Jiao Tong University
ABSTRACT
The Resistive Random-Access-Memory (ReRAM) in crossbar structure has shown great potential in accelerating the vector-matrix multiplication, owing to the fascinating computing complexity reduction (from O(n2) to O(1)). Nevertheless, the ReRAM cells still encounter device programming variation and resistance drifting during computation (known as read disturbance), which significantly hamper its analog computing precision. Inspired by prior precise memory programming works, we propose a Self-Terminating Write (STW) circuit for Multi-Level Cell (MLC) ReRAM. In order to minimize the area overhead, the design heavily reuses inherent computing peripherals (e.g., Analog-to-Digital Converter and Trans-Impedance Amplifier) in conventional dot-product engine. Thanks to the fast and precise programming capability of our design, the ReRAM cell can possess 4 linear distributed conductance levels, with minimum latency used for intermediate resistance refreshing. Our comprehensive cross-layer (device/circuit/architecture) simulation indicates that the proposed MLC STW scheme can effectively obtain 2-bit precision via a single programming pulse. Besides, our design outperforms the prior write&verify schemes by 4.7× and 2× in programming latency and energy, respectively.
Keywords: ReRAM, Programming, Multi-Level Cell, Read Disturbance.
