A Pluggable Vector Unit for RISC-V Vector Extension
Vincenzo Maisto1,a,b and Alessandro Cilardo2
1Hensoldt Cyber GmbH, and University of Naples Federico II Taufkirchen, Germany and, Naples, Italy
avincenzo.maisto@hensoldt-cyber.de
bvincenzo.maisto@studenti.unina.it
2University of Naples Federico II Naples, Italy
acilardo@unina.it
ABSTRACT
Vector extensions have become increasingly important for accelerating data-parallel applications in areas like multimedia, data-streaming, and Machine Learning. This interactive presentation introduces a microarchitectural design of a vector unit compliant with the RISC-V vector extension v1.0. While we targeted a specific core for demonstration, CVA6, our architecture is designed so as to ensure extensibility, maintainability, and reusability in other cores. Furthermore, as a distinctive feature, we support speculative execution and precise vector traps. The paper provides an overview of the main motivation, design choices, and implementation details, followed by a qualitative and quantitative discussion of the results collected from the synthesis of the extended CVA6 RISC-V core.
Keywords: RISC-V, vector extension, open-source hardware, FPGA, UltraScale+.
