Are Analytical Techniques Worthwhile for Analog IC Placement?
Yishuang Lin1,a, Yaguang Li1,b, Donghao Fang1,c, Meghna Madhusudan2,e, Sachin S. Sapatnekar2,f, Ramesh Harjani2,g and Jiang Hu1,d
1Texas A&M University
alionlin@tamu.edu
bliyg@tamu.edu
cdonghao@tamu.edu
djianghu@tamu.edu
2University of Minnesota
emadhu028@umn.edu
fsachin@umn.edu
gharjani@umn.edu
ABSTRACT
Analytical techniques have long been a prevailing approach to digital IC placement due to their advantage in handling large-sized problems. Recently, they have been adopted for analog IC placement, an area where prior methods were mostly based on simulated annealing. However, a comparative study between the two classes of approaches is lacking. Moreover, the effectiveness of different analytical techniques is not clear. This work attempts to shed light on both issues by studying existing methods and developing a new analytical technique. Since prior analytical methods have not addressed circuit performance, a critical concern for automated analog layout, this work also extends the new analytical placer for performance-driven placement. Experiments on various test circuits show that for a conventional performance-oblivious formulation, the proposed analytical technique achieves 55× speedup and 12% wirelength reduction compared to simulated annealing. For performancedriven placement, the proposed technique outperforms simulated annealing in terms of circuit performance, area, and runtime. Moreover, the proposed technique generally provides better solution quality than an alternative analytical technique.
