NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network
Fuping Li1,2,a, Ying Wang1,2,4,b, Cheng Liu1,2,c, Huawei Li1,2,d and Xiaowei Li1,2,e
1SKLCA, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
2University of Chinese Academy of Sciences, Beijing, China
3Peng Cheng Laboratory, Shenzhen, China
4Zhejiang Laboratory, Hangzhou, China
alifuping20s@ict.ac.cn
bwangying2009@ict.ac.cn
cliucheng@ict.ac.cn
dlihuawei@ict.ac.cn
elxw@ict.ac.cn
ABSTRACT
Network-on-Chips (NoCs) have been viewed as a promising alternative to traditional on-chip communication architecture for the increasing number of IPs in modern chips. To support the vast design space exploration of application-specific NoC characteristics with arbitrary topologies, in this paper, we propose a fast estimation framework to predict power, performance, and area (PPA) of NoCs based on graph neural networks (GNNs). We present a general way of modeling the application and the NoC with user-defined parameters as an attributed graph, which can be learned by the GNN model. Experimental results show that on the unseen realistic applications, the proposed method achieves the accuracy of 97.36% on power estimation, 97.83% on area estimation, and improves the accuracy of the network-level and system-level performance predictor over the topology-constrained baseline method by 6.52% and 4.73% respectively.
Keywords: Network-On-Chip, PPA Prediction, Graph Neural Network.
