Scalable Hardware Acceleration of Non-Maximum Suppression
Chunyun Chen1,a, Tianyi Zhang2,f, Zehui Yu1,b, Adithi Raghuraman1,c, Shwetalaxmi Udayan1,d, Jie Lin2,g and Mohamed M. Sabry Aly1,d
1Nanyang Technological University, Singapore
aCHUNYUN001@ntu.edu.sg
bYUZE0004@ntu.edu.sg
cADITHI001@ntu.edu.sg
dSHWETALA001@ntu.edu.sg
emsabry@ntu.edu.sg
2Institute for Infocomm Research, A*STAR, Singapore
fZhang_Tianyi@i2r.a-star.edu.sg
glin-j@i2r.a-star.edu.sg
ABSTRACT
Non-maximum Suppression (NMS) in one- and twostage object detection deep neural networks (e.g., SSD and Faster- RCNN) is becoming the computation bottleneck. In this paper, we introduce a hardware acceleration for the scalable PSRRMaxpoolNMS algorithm. Our architecture shows 75:0× and 305× speedups compared to the software implementation of the PSRRMaxpoolNMS as well as the hardware implementations of GreedyNMS, respectively, while simultaneously achieving comparable Mean Average Precision (mAP) to software-based floating-point implementations. Our architecture is 13:4× faster than the stateof- the-art NMS one. Our accelerator supports both one- and twostage detectors, while supporting very high input resolutions (i.e., FHD)—essential input size for better detection accuracy.
Keywords: deep learning, Non-maximum Suppression, parallel computing, object detection.
