Eva-CAM: A Circuit/Architecture-Level Evaluation Tool for General Content Addressable Memories
Liu Liu1, Mohammad Mehdi Sharifi1, Ramin Rajaei1, Arman Kazemi1,
Kai Ni2, Xunzhao Yin3, Michael Niemier1 and Xiaobo Sharon Hu1
1University of Notre Dame, USA
2Rochester Institute of Technology, USA
3Zhejiang University, China
ABSTRACT
Content addressable memories (CAMs), a specialpurpose in-memory computing (IMC) unit, support parallel searches directly in memory. There is growing interest in CAMs for data-intensive applications such as machine learning and bioinformatics. The design space for CAMs is rapidly expanding. In addition to traditional ternary CAMs (TCAMs), analog CAM (ACAM) and multi-bit CAM (MCAM) designs based on various non-volatile memory (NVM) devices have been recently introduced and may offer higher density, better energy efficiency, and non-volatility. Furthermore, aside from the widely-used exact match based search, CAM-based approximate matches have been proposed to further extend the utility of CAMs to new application spaces. For this memory architecture, evaluating different CAM design options for a given application is becoming more challenging. This paper presents Eva-CAM, a circuit/architecturelevel modeling and evaluation tool for CAMs. Eva-CAM supports TCAM, ACAM, and MCAM designs implemented in non-volatile memories, for both exact and approximate match types. It also allows for the exploration of CAM array structures and sensing circuits. Eva-CAM has been validated with HSPICE simulation results and chip measurements. A comprehensive case study is described for FeFET CAM design space exploration.
