PATS: Taming Bandwidth Contention between Persistent and Dynamic Memories
Shucheng Wang1, Qiang Cao1, Ziyi Lu1, Hong Jiang3 and Yuanyuan Dong2
1Wuhan National Laboratory for Optoelectronics, HUST
2Alibaba Group
3Department of Computer Science and Engineering, University of Texas at Arlington
ABSTRACT
Emerging persistent memory (PM) with fast persistence and byte-addressability physically shares the memory channel with DRAM-based main memory. We experimentally uncover that the throughput of application accessing DRAM collapses when multiple threads access PM due to head-of-line blockage in the memory controller within CPU. To address this problem, we design a PM-Accessing Thread Scheduling (PATS) mechanism that is guided by a contention model, to adaptively tune the maximum number of contention-free concurrent PMthreads. Experimental results show that even with 14 concurrent threads accessing PM, PATS is able to allow only up to 8% decrease in the DRAM-throughput of the front-end applications (e.g., Memcached), gaining 1.5x PM-throughput speedup over the default configuration.
Keywords: Persistent Memory, Memory Contention, Thread Scheduling.
