Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor
Dongyun Kama, Jung Gyu Minb, Jongho Yoonc, Sunmean Kimd, Seokhyeong Kange and Youngjoo Leef
Department of Electrical Engineering Pohang University of Science and Technology, Pohang, South Korea
arkaehddbs@postech.ac.kr
bmjg1104@postech.ac.kr
cyoonjongho99@postech.ac.kr
dsunmean@postech.ac.kr
eshkang@postech.ac.kr
fyoungjoo.lee@postech.ac.kr
ABSTRACT
In this paper, we introduce the design and verification frameworks for developing a fully-functional emerging ternary processor. Based on the existing compiling environments for binary processors, for the given ternary instructions, the software-level framework provides an efficient way to convert the given programs to the ternary assembly codes. We also present a hardware-level framework to rapidly evaluate the performance of a ternary processor implemented in arbitrary design technology. As a case study, the fully-functional 9-trit advanced RISC-based ternary (ART-9) core is newly developed by using the proposed frameworks. Utilizing 24 custom ternary instructions, the 5-stage ART-9 prototype architecture is successfully verified by a number of test programs including dhrystone benchmark in a ternary domain, achieving the processing efficiency of 57.8 DMIPS/W and 3.06×106 DMIPS/W in the FPGA-level ternary-logic emulations and the emerging CNTFET ternary gates, respectively.
Keywords: Ternary processor, Instruction set architecture, RISC, Emerging computer design, Multi-valued logic circuits.
