Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators
Yu Zenga, Aarti Guptab and Sharad Malikc
Princeton University, Princeton, USA
ayuzeng@princeton.edu
baartig@cs.princeton.edu
csharad@princeton.edu
ABSTRACT
Hardware platforms comprise general-purpose processors and application-specific accelerators. Unlike processors, application-specific accelerators often do not have clearly specified architecture-level models/specifications (the instruction set architecture or ISA). This poses challenges to the development and verification/validation of firmware/software for these accelerators. Manually writing architecture-level models takes great effort and is error-prone. When Register-Transfer Level (RTL) designs are available, they can be a source from which to automatically derive the architecture-level models. In this work, we propose an approach for automatically generating architecture-level models for processors as well as accelerators from their RTL designs. In previous work we showed how to automatically extract the architectural state variables (ASVs) from RTL designs. (These are the state variables that are persistent across instructions.) In this work we present an algorithm for generating the update functions of the model: how the ASVs and outputs are updated by each instruction. Experiments on several processors and accelerators demonstrate that our approach can cover a wide range of hardware features and generate highquality architecture-level models within reasonable time.
Keywords: Hardware Modelling, Accelerators, Architectural Abstraction.
