Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
Niklas Bruns1,a, Vladimir Herdt1,2,b, Eyck Jentzsch3 and Rolf Drechsler1,2,c
1Institute of Computer Science, University of Bremen, 28359 Bremen, Germany
anbruns@uni-bremen.de
2Cyber-Physical Systems, DFKI GmbH, 28359 Bremen, Germany
bvherdt@uni-bremen.de
cdrechsler@uni-bremen.de
3MINRES Technologies GmbH, 85579 Neubiberg, Germany
eyck@minres.com
ABSTRACT
We propose a novel cross-level verification approach for processor verification at the Register-Transfer Level (RTL). The foundation is a randomized coverage-guided instruction stream generator that produces one endless and unrestricted instruction stream that evolves dynamically at runtime. We leverage an Instruction Set Simulator (ISS) as a reference model in a tight co-simulation setting. Coverage information is continuously updated based on the execution state of the ISS and we employ Coverage-guided Aging to smooth out the coverage distribution of the randomized instruction stream over the time. In combination, this enables a broad and deep coverage to find intricate cornercase bugs in the RTL processor. Our case study with an industrial pipelined 32 bit RISC-V processor demonstrate the effectiveness of our approach.
