Test Pattern Generation for Approximate Circuits Based on Boolean Satisfiability
Anteneh Gebregiorgisa and Mehdi B. Tahoorib
Chair of Dependable Nano Computing (CDNC) Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany
aanteneh.gebregiorgis@kit.edu
bmehdi.tahoori@kit.edu
ABSTRACT
Approximate computing has gained growing attention as it provides trade-off between output quality and computation effort for inherent error tolerant applications such as recognition, mining, and media processing applications. As a result, several approximate hardware designs have been proposed in order to harness the benefits of approximate computing. While these circuits are subjected to manufacturing defects and runtime failures, the testing methods should be aware of their approximate nature. In this paper, we propose an automatic test pattern generation methodology for approximate circuits based on boolean satisfiability, which is aware of output quality and approximable vs non-approximable faults. This allows us to significantly reduce the number of faults to be tested, and test time accordingly, without sacrificing the output quality or test coverage. Experimental results show that, the proposed approach can reduce the fault list by 2.85× on average while maintaining high fault coverage.
